Xilinx Virtex-6 Manual page 165

Note You cannot have an active set and an active reset in this component. One or both of the signals R and S
must be tied to ground.
Design Entry Method
Instantiation
Inference
CORE Generator™ and wizards
Macro support
Available Attributes
Data
Attribute Type
DDR_CLK_EDGE String
INIT_Q1 Binary
INIT_Q2 Binary
SRTYPE String
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- IDDR: Double Data Rate Input Register with Set, Reset
-- and Clock Enable.
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
IDDR_inst : IDDR
generic map (
DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE", "SAME_EDGE"
INIT_Q1 => '0', -- Initial value of Q1: '0' or '1'
INIT_Q2 => '0', -- Initial value of Q2: '0' or '1'
SRTYPE => "SYNC") -- Set/Reset type: "SYNC" or "ASYNC"
port map (
Q1 => Q1, -- 1-bit output for positive edge of clock
Q2 => Q2, -- 1-bit output for negative edge of clock
C => C, -- 1-bit clock input
CE => CE, -- 1-bit clock enable input
D => D, -- 1-bit DDR data input
R => R, -- 1-bit reset
S => S -- 1-bit set
);
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Allowed Values Default
"OPPOSITE_EDGE", "OPPOSITE_
"SAME_EDGE", EDGE"
"SAME_EDGE_
PIPELINED"
0, 1 0
0, 1 0
"SYNC" or "ASYNC" "SYNC"
-- or "SAME_EDGE_PIPELINED"
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Chapter 4: About Design Elements
Recommended
No
No
No
Description
Sets the IDDR mode of operation with
respect to clock edge.
Initial value on the Q1 pin after
configuration startup or when GSR is
asserted.
Initial value on the Q2 pin after
configuration startup or when GSR is
asserted.
Set/reset type selection. "SYNC" specifies
the behavior of the reset (R) and set (S)
pins to be synchronous to the positive edge
of the C clock pin. "ASYNC" specifies an
asynchronous set/reset function.
165