Xilinx Virtex-6 Manual page 306

Chapter 4: About Design Elements
Verilog Instantiation Template
// RAM32X1D: 32 x 1 positive edge write, asynchronous read dual-port distributed RAM
// Virtex-6
// Xilinx HDL Libraries Guide, version 14.5
RAM32X1D #(
.INIT(32'h00000000) // Initial contents of RAM
) RAM32X1D_inst (
.DPO(DPO), // Read-only 1-bit data output
.SPO(SPO), // Rw/ 1-bit data output
.A0(A0), // Rw/ address[0] input bit
.A1(A1), // Rw/ address[1] input bit
.A2(A2), // Rw/ address[2] input bit
.A3(A3), // Rw/ address[3] input bit
.A4(A4), // Rw/ address[4] input bit
.D(D), // Write 1-bit data input
.DPRA0(DPRA0), // Read-only address[0] input bit
.DPRA1(DPRA1), // Read-only address[1] input bit
.DPRA2(DPRA2), // Read-only address[2] input bit
.DPRA3(DPRA3), // Read-only address[3] input bit
.DPRA4(DPRA4), // Read-only address[4] input bit
.WCLK(WCLK), // Write clock input
.WE(WE) // Write enable input
);
// End of RAM32X1D_inst instantiation
For More Information
See the Virtex-6 FPGA User Documentation (User Guides and Data
306
Sheets).
Virtex-6 Libraries Guide for HDL Designs
www.xilinx.com UG623 (v 14.5) March 20, 2013