Xilinx Virtex-6 Manual page 56

Chapter 2: About Unimacros
Available Attributes
Attribute Data Type
WIDTH_A Integer
WIDTH_B Integer
LATENCY Integer
DEVICE String
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- MULT_MACRO: Multiply Function implemented in a DSP48E
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
MULT_MACRO_inst : MULT_MACRO
generic map (
DEVICE => "VIRTEX6",
LATENCY => 3,
WIDTH_A => 18,
WIDTH_B => 18)
port map (
P => P, -- Multiplier output bus, width determined by WIDTH_P generic
A => A, -- Multiplier input A bus, width determined by WIDTH_A generic
B => B, -- Multiplier input B bus, width determined by WIDTH_B generic
CE => CE, -- 1-bit active high input clock enable
CLK => CLK, -- 1-bit positive edge clock input
RST => RST -- 1-bit input active high reset
);
-- End of MULT_MACRO_inst instantiation
Verilog Instantiation Template
// MULT_MACRO: Multiply Function implemented in a DSP48E
// Virtex-6
// Xilinx HDL Libraries Guide, version 14.5
MULT_MACRO #(
.DEVICE("VIRTEX6"), // Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6"
.LATENCY(3), // Desired clock cycle latency, 0-4
.WIDTH_A(18), // Multiplier A-input bus width, 1-25
.WIDTH_B(18) // Multiplier B-input bus width, 1-18
) MULT_MACRO_inst (
.P(P), // Multiplier output bus, width determined by WIDTH_P parameter
.A(A), // Multiplier input A bus, width determined by WIDTH_A parameter
.B(B), // Multiplier input B bus, width determined by WIDTH_B parameter
.CE(CE), // 1-bit active high input clock enable
.CLK(CLK), // 1-bit positive edge clock input
56
Allowed Values
1 to 25
1 to 18
0, 1, 2, 3, 4
"VIRTEX5",
"VIRTEX6",
"SPARTAN6"
-- Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6"
-- Desired clock cycle latency, 0-4
-- Multiplier A-input bus width, 1-25
-- Multiplier B-input bus width, 1-18
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Default Description
25
Controls the width of A input.
18
Controls the width of B input.
3
Number of pipeline registers
• 1 - MREG == 1
• 2 - AREG == BREG == 1 and MREG
== 1 or MREG == 1 and PREG == 1
• 3 - AREG == BREG == 1 and MREG
== 1 and PREG == 1
• 4 - AREG == BREG == 2 and MREG
== 1 and PREG == 1
VIRTEX6" Target hardware architecture.
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013