Xilinx Virtex-6 Manual page 154

Chapter 4: About Design Elements
IBUFDS_GTXE1
Primitive: Differential Clock Input for the Transceiver Reference Clocks
Introduction
This component is the differential clock input for the transceiver reference clocks. It can also drive other
clock resources such as BUFG/MMCM as well as the reference clock inputs of the GT. It typically connects
to the MGTREFCLKRX/TX pins of the 4 GTXE1 in the quad associated with the IBUFDS_GTXE1, to the
NORTHREFCLKRX/TX of the 4 GTXE1 in the quad above, or to the SOUTHREFCLKRX/TX pins of the 4 GTXE1
in the quad below.
There are multiple destination pins in Virtex®-6 devices that the IBUFDS_GTXE1 element could connect to. If
one reference clock on the GT is connected, SW has full control and can route and connect to the GT on any of the
pins based on the most optimal route. If multiple clocks are connected to the GT then SW will route each IBUFDS
to the indicated pin on the GT. So the O pin on the IBUFDS_GTXE1 connects to either the MGTREFCLKRX/TX or
the NORTH/SOUTHREFCLKRX/TX pins on the GT.
Note The RX and TX MUXes can be chosen independently, but the routes are shared on physical silicon.
Design Entry Method
To instantiate this component, use the RocketIO™ wizard or an associated core containing the component. Xilinx
does not recommend direct instantiation of this component.
For More Information
See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).
Virtex-6 Libraries Guide for HDL Designs
154 www.xilinx.com UG623 (v 14.5) March 20, 2013