Xilinx Virtex-6 Manual page 65

DO => DO,
EMPTY => EMPTY,
FULL => FULL,
RDCOUNT => RDCOUNT,
RDERR => RDERR,
WRCOUNT => WRCOUNT,
WRERR => WRERR,
CLK => CLK,
DI => DI,
RDEN => RDEN,
RST => RST,
WREN => WREN
);
-- End of FIFO_SYNC_MACRO_inst instantiation
Verilog Instantiation Template
// FIFO_SYNC_MACRO: Synchronous First-In, First-Out (FIFO) RAM Buffer
// Virtex-6
// Xilinx HDL Libraries Guide, version 14.5
/////////////////////////////////////////////////////////////////
// DATA_WIDTH | FIFO_SIZE | FIFO Depth | RDCOUNT/WRCOUNT Width //
// ===========|===========|============|=======================//
// 37-72 | "36Kb"
// 19-36 | "36Kb"
// 19-36 | "18Kb"
// 10-18 | "36Kb"
// 10-18 | "18Kb"
// 5-9 | "36Kb"
// 5-9 | "18Kb"
// 1-4 | "36Kb"
// 1-4 | "18Kb"
/////////////////////////////////////////////////////////////////
FIFO_SYNC_MACRO #(
.DEVICE("VIRTEX6"), // Target Device: "VIRTEX5", "VIRTEX6"
.ALMOST_EMPTY_OFFSET(9'h080), // Sets the almost empty threshold
.ALMOST_FULL_OFFSET(9'h080),
.DATA_WIDTH(0), // Valid values are 1-72 (37-72 only valid when FIFO_SIZE="36Kb")
.DO_REG(0), // Optional output register (0 or 1)
.FIFO_SIZE ("18Kb") // Target BRAM: "18Kb" or "36Kb"
) FIFO_SYNC_MACRO_inst (
.ALMOSTEMPTY(ALMOSTEMPTY), // 1-bit output almost empty
.ALMOSTFULL(ALMOSTFULL),
.DO(DO),
.EMPTY(EMPTY),
.FULL(FULL),
.RDCOUNT(RDCOUNT),
.RDERR(RDERR),
.WRCOUNT(WRCOUNT),
.WRERR(WRERR),
.CLK(CLK),
.DI(DI),
.RDEN(RDEN),
.RST(RST),
.WREN(WREN)
);
// End of FIFO_SYNC_MACRO_inst instantiation
For More Information
See the Virtex-6 FPGA User Documentation (User Guides and Data
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
-- Output data, width defined by DATA_WIDTH parameter
-- 1-bit output empty
-- 1-bit output full
-- Output read count, width determined by FIFO depth
-- 1-bit output read error
-- Output write count, width determined by FIFO depth
-- 1-bit output write error
-- 1-bit input clock
-- Input data, width defined by DATA_WIDTH parameter
-- 1-bit input read enable
-- 1-bit input reset
-- 1-bit input write enable
| 512 | 9-bit
| 1024 | 10-bit
| 512 | 9-bit
| 2048 | 11-bit
| 1024 | 10-bit
| 4096 | 12-bit
| 2048 | 11-bit
| 8192 | 13-bit
| 4096 | 12-bit
// Sets almost full threshold
// 1-bit output almost full
// Output data, width defined by DATA_WIDTH parameter
// 1-bit output empty
// 1-bit output full
// Output read count, width determined by FIFO depth
// 1-bit output read error
// Output write count, width determined by FIFO depth
// 1-bit output write error
// 1-bit input clock
// Input data, width defined by DATA_WIDTH parameter
// 1-bit input read enable
// 1-bit input reset
// 1-bit input write enable
www.xilinx.com
Chapter 2: About Unimacros
//
//
//
//
//
//
//
//
//
Sheets).
65