Xilinx Virtex-6 Manual page 71

Design Element
CARRY4
CFGLUT5
LUT1
LUT1_D
LUT1_L
LUT2
LUT2_D
LUT2_L
LUT3
LUT3_D
LUT3_L
LUT4
LUT4_D
LUT4_L
LUT5
LUT5_D
LUT5_L
LUT6
LUT6_2
LUT6_D
LUT6_L
MUXF7
MUXF7_D
MUXF7_L
MUXF8
MUXF8_D
MUXF8_L
SRL16E
SRLC32E
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Slice/CLB Primitives
Description
Primitive: Fast Carry Logic with Look Ahead
Primitive: 5-input Dynamically Reconfigurable Look-Up
Table (LUT)
Macro: 1-Bit Look-Up Table with General Output
Macro: 1-Bit Look-Up Table with Dual Output
Macro: 1-Bit Look-Up Table with Local Output
Macro: 2-Bit Look-Up Table with General Output
Macro: 2-Bit Look-Up Table with Dual Output
Macro: 2-Bit Look-Up Table with Local Output
Macro: 3-Bit Look-Up Table with General Output
Macro: 3-Bit Look-Up Table with Dual Output
Macro: 3-Bit Look-Up Table with Local Output
Macro: 4-Bit Look-Up-Table with General Output
Macro: 4-Bit Look-Up Table with Dual Output
Macro: 4-Bit Look-Up Table with Local Output
Primitive: 5-Input Lookup Table with General Output
Primitive: 5-Input Lookup Table with General and Local
Outputs
Primitive: 5-Input Lookup Table with Local Output
Primitive: 6-Input Lookup Table with General Output
Primitive: Six-input, 2-output, Look-Up Table
Primitive: 6-Input Lookup Table with General and Local
Outputs
Primitive: 6-Input Lookup Table with Local Output
Primitive: 2-to-1 Look-Up Table Multiplexer with General
Output
Primitive: 2-to-1 Look-Up Table Multiplexer with Dual
Output
Primitive: 2-to-1 look-up table Multiplexer with Local
Output
Primitive: 2-to-1 Look-Up Table Multiplexer with General
Output
Primitive: 2-to-1 Look-Up Table Multiplexer with Dual
Output
Primitive: 2-to-1 Look-Up Table Multiplexer with Local
Output
Primitive: 16-Bit Shift Register Look-Up Table (LUT) with
Clock Enable
Primitive: 32 Clock Cycle, Variable Length Shift Register
Look-Up Table (LUT) with Clock Enable
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Chapter 3: Functional Categories
71