Xilinx Virtex-6 Manual page 163

Verilog Instantiation Template
// ICAP_VIRTEX6: Internal Configuration Access Port
// Virtex-6
// Xilinx HDL Libraries Guide, version 14.5
ICAP_VIRTEX6 #(
.DEVICE_ID(0'h4244093),
.ICAP_WIDTH("X8"),
.SIM_CFG_FILE_NAME("NONE")
)
ICAP_VIRTEX6_inst (
.BUSY(BUSY), // 1-bit output: Busy/Ready output
.O(O), // 32-bit output: Configuration data output bus
.CLK(CLK), // 1-bit input: Clock Input
.CSB(CSB), // 1-bit input: Active-Low ICAP input Enable
.I(I), // 32-bit input: Configuration data input bus
.RDWRB(RDWRB) // 1-bit input: Read/Write Select input
);
// End of ICAP_VIRTEX6_inst instantiation
For More Information
See the Virtex-6 FPGA User Documentation (User Guides and Data
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
// Specifies the pre-programmed Device ID value
// Specifies the input and output data width to be used with the
// ICAP_VIRTEX6.
// Specifies the Raw Bitstream (RBT) file to be parsed by the simulation
// model
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