Xilinx Virtex-6 Manual page 70

Chapter 3: Functional Categories
Design Element
RAM32X2S
RAM64M
RAM64X1D
RAM64X1S
RAM64X1S_1
RAMB18E1
RAMB36E1
ROM128X1
ROM256X1
ROM32X1
ROM64X1
Design Element
FDCE
FDPE
FDRE
FDSE
IDDR
IDDR_2CLK
LDCE
LDPE
ODDR
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Description
Primitive: 32-Deep by 2-Wide Static Synchronous RAM
Primitive: 64-Deep by 4-bit Wide Multi Port Random
Access Memory (Select RAM)
Primitive: 64-Deep by 1-Wide Dual Port Static Synchronous
RAM
Primitive: 64-Deep by 1-Wide Static Synchronous RAM
Primitive: 64-Deep by 1-Wide Static Synchronous RAM
with Negative-Edge Clock
Primitive: 18K-bit Configurable Synchronous Block RAM
Primitive: 36K-bit Configurable Synchronous Block RAM
Primitive: 128-Deep by 1-Wide ROM
Primitive: 256-Deep by 1-Wide ROM
Primitive: 32-Deep by 1-Wide ROM
Primitive: 64-Deep by 1-Wide ROM
Registers/Latches
Description
Primitive: D Flip-Flop with Clock Enable and
Asynchronous Clear
Primitive: D Flip-Flop with Clock Enable and
Asynchronous Preset
Primitive: D Flip-Flop with Clock Enable and Synchronous
Reset
Primitive: D Flip-Flop with Clock Enable and Synchronous
Set
Primitive: Input Dual Data-Rate Register
Primitive: Input Dual Data-Rate Register with Dual Clock
Inputs
Primitive: Transparent Data Latch with Asynchronous
Clear and Gate Enable
Primitive: Transparent Data Latch with Asynchronous
Preset and Gate Enable
Primitive: Dedicated Dual Data Rate (DDR) Output
Register
Virtex-6 Libraries Guide for HDL Designs
www.xilinx.com UG623 (v 14.5) March 20, 2013