Xilinx Virtex-6 Manual page 366

Chapter 4: About Design Elements
Design Entry Method
Instantiation
Inference
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If instantiated, the following connections should be made to this component:
• Connect the CLK input to the desired clock source, the D input to the data source to be shifted/stored and the
Q output to either an FDCPE or an FDRSE input or other appropriate data destination.
• The CE clock enable pin can be connected to a clock enable signal in the design or else tied to a logic one
if not used.
• The 5-bit A bus can either be tied to a static value between 0 and 31 to signify a fixed 1 to 32 bit static shift
length, or else it can be tied to the appropriate logic to enable a varying shift depth anywhere between 1
and 32 bits.
• If you want to create a longer shift length than 32, connect the Q31 output pin to the D input pin of a
subsequent SRLC32E to cascade and create larger shift registers.
• It is not valid to connect the Q31 output to anything other than another SRLC32E.
• The selectable Q output is still available in the cascaded mode, if needed.
• An optional INIT attribute consisting of a 32-bit Hexadecimal value can be specified to indicate the initial
shift pattern of the shift register.
• (INIT[0] will be the first value shifted out.)
Available Attributes
Attribute Type
INIT Hexa-
decimal
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- SRLC32E: 32-bit variable length shift register LUT
-- with clock enable
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
SRLC32E_inst : SRLC32E
generic map (
INIT => X"00000000")
port map (
Q => Q, -- SRL data output
Q31 => Q31, -- SRL cascade output pin
A => A, -- 5-bit shift depth select input
CE => CE, -- Clock enable input
CLK => CLK, -- Clock input
D => D -- SRL data input
);
-- End of SRLC32E_inst instantiation
366
Yes
Recommended
No
No
Allowed Values Default
Any 32-Bit Value All zeros
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Description
Specifies the initial shift pattern of the
SRLC32E.
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013