Xilinx Virtex-6 Manual page 88

Chapter 4: About Design Elements
BUFGMUX_1
Primitive: Global Clock MUX Buffer with Output State 1
Introduction
This design element is a multiplexed global clock buffer that can select between two input clocks: I0 and I1.
When the select input (S) is Low, the signal on I0 is selected for output (0). When the select input (S) is High, the
signal on I1 is selected for output.
This design element is distinguished from BUFGMUX by the state the output assumes when that output switches
between clocks in response to a change in its select input. BUFGMUX assumes output state 0 and BUFGMUX_1
assumes output state 1.
Logic Table
Inputs
I0
I0
X
X
X
Port Descriptions
Port
I0
I1
O
S
Design Entry Method
Instantiation
Inference
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Macro support
88
I1
X
I1
X
X
Direction
Input
Input
Output
Input
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S
0
1
↑
↓
Width
1
1
1
1
Yes
Recommended
No
No
Virtex-6 Libraries Guide for HDL Designs
Outputs
O
I0
I1
1
1
Function
Clock0 input
Clock1 input
Clock MUX output
Clock select input
UG623 (v 14.5) March 20, 2013