Xilinx Virtex-6 Manual page 275

OBUFDS
Primitive: Differential Signaling Output Buffer
Introduction
This design element is a single output buffer that supports low-voltage, differential signaling (1.8 v CMOS).
OBUFDS isolates the internal circuit and provides drive current for signals leaving the chip. Its output is
represented as two distinct ports (O and OB), one deemed the "master" and the other the "slave." The master and
the slave are opposite phases of the same logical signal (for example, MYNET and MYNETB).
Logic Table
Inputs
I
0
1
Port Descriptions
Port Direction
O Output
OB Output
I Input
Design Entry Method
Instantiation
Inference
CORE Generator™ and wizards
Macro support
Available Attributes
Data
Attribute Type
IOSTANDARD String
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Outputs
O
0
1
Width
1
1
1
Recommended
No
No
No
Allowed
Values Default
"DEFAULT"
See Data Sheet
www.xilinx.com
Chapter 4: About Design Elements
OB
1
0
Function
Diff_p output (connect directly to top level port)
Diff_n output (connect directly to top level port)
Buffer input
Description
Assigns an I/O standard to the element.
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