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Xilinx Virtex-4 RocketIO Manuals
Manuals and User Guides for Xilinx Virtex-4 RocketIO. We have
3
Xilinx Virtex-4 RocketIO manuals available for free PDF download: User Manual, Configuration User Manual
Xilinx Virtex-4 RocketIO User Manual (339 pages)
Multi-Gigabit Transceiver
Brand:
Xilinx
| Category:
Transceiver
| Size: 7.93 MB
Table of Contents
Table of Contents
7
Revision History
3
: Analog and Board Design Considerations
17
Preface: about this Guide
27
MGT Features
27
User Guide Organization
28
Additional Resources
29
Logical / Mathematical Operators
29
Related Information
29
User Guide Conventions
29
Comma Definition
30
Jitter Definition
30
MGT Definition
30
Port and Attribute Names
30
Total Jitter (DJ + RJ) Definition
30
Typographical
31
FPGA Level Design
33
Section I
33
Chapter 1 : Rocketio Transceiver Overview
35
Basic Architecture and Capabilities
35
Figure 1-1: Rocketio Multi-Gigabit Transceiver Block Diagram
36
Available Ports
39
Configuring the Rocketio MGT
39
Attributes
48
Byte Mapping
60
Chapter 2: Clocking, Timing, and Resets
61
Clock Distribution
61
Column
61
Mgt
61
Tile
61
Figure 2-1: MGT Column Clocking
62
GT11CLK_MGT and Reference Clock Routing
63
MGT Clock Ports and Attributes
64
Common Reference Clock Use Models
66
High-Speed Dedicated MGT Clocks
66
Fabric Clocks
67
PMA Transmit Clocks
68
PMA Receive Clocks
70
RX and TX PLL Voltage-Controlled Oscillator (VCO) Operating Frequency
72
Figure 2-6: Transmitter and Receiver Line Rates
73
PMA/PCS Clocking Domains and Data Paths
74
Figure 2-7: PCS Receive Clocking Domains and Datapaths
74
PMA Configurations
75
Figure 2-9: Low-Latency Clocking
76
Common MGT Clocking Use Cases
76
Setting the Clocking Options
77
Figure 2-10: DCM Clocking
77
Figure 2-11: Receive Clocking Decision Flow (Page 1 of 2)
78
Figure 2-11 (Cont'D): Receive Clocking Decision Flow (Page 2 of 2)
79
Figure 2-12: Transmit Clocking Decision Flow (Page 1 of 2)
80
Figure 2-12 (Cont'D): Transmit Clocking Decision Flow (Page 2 of 2)
81
Special Clocking Considerations
82
RXCLKSTABLE and TXCLKSTABLE
82
Resets
83
Rxpmareset
83
Txpmareset
83
Rxreset
84
Txreset
84
CRC Reset
85
Resetting the Transceiver
85
Transmit Reset Sequence: TX Buffer Used
85
Figure 2-14: Flow Chart of TX Reset Sequence Where TX Buffer Is Used
86
Figure 2-15: Resetting the Transmitter Where TX Buffer Is Used
87
Figure 2-16: Flow Chart of TX Reset Sequence Where TX Buffer Is Bypassed
88
Transmit Reset Sequence: TX Buffer Bypassed
88
And Tx_Align_Err Is Not Used
91
Figure 2-18: Resetting the Transmitter Where TX Buffer Is Bypassed
93
Receive Reset Sequence: RX Buffer Used
93
Figure 2-19: Flow Chart of Receiver Reset Sequence Where RX Buffer Is Used
94
Figure 2-20: Resetting the Receiver in Digital CDR Mode Where RX Buffer Is Used
95
Figure 2-21: Resetting the Receiver in Analog CDR Mode Where RX Buffer Is Used
96
Receive Reset Sequence: RX Buffer Bypassed
96
Figure 2-22: Flow Chart of Receiver Reset Sequence Where RX Buffer Is Bypassed
97
Reset Considerations
99
RX Reset Sequence Background
100
Chapter 3: PCS Digital Design Considerations
101
Top-Level Architecture
101
Receive Architecture
101
Transmit Architecture
101
Fabric Interface Synchronicity
102
RX Buffer
102
Bus Interface
103
External Bus Width Configuration (Fabric Interface)
103
Internal Bus Width Configuration
104
Fabric Interface Functionality
105
Figure 3-5: Fabric Interface Timing
106
PCS Bypass Byte Mapping
107
8B/10B Encoding/Decoding
108
Encoder
109
TXCHARDISPVAL and TXCHARDISPMODE
110
Txcharisk
111
Txkerr
111
Txrundisp
111
Decoder
112
RXCHARISK and RXRUNDISP
113
Rxdisperr
113
Rxchariscomma
114
Rxnotintable
114
Non-Standard Running Disparity Example
115
Receiving Vitesse Channel Bonding Sequence
115
Transmitting Vitesse Channel Bonding Sequence
115
Symbol Alignment and Detection (Comma Detection)
116
Bypassing
116
Summary
116
10-Bit Alignment for 8B/10B Encoded Data
117
8-Bit / 10-Bit Alignment
117
Determining Barrel Shifter Position
118
Figure 3-13: 6-Bit Alignment Mux Position
118
SONET Alignment
119
Figure 3-16: SONET Alignment Sequence (2-Byte External Data Interface Width)
120
Alignment Status
122
Align_Comma_Word = 1
122
Byte Alignment
122
Rxslide
123
Clock Correction
123
Append/Remove Idle Clock Correction
123
Clock Correction Sequences
124
Clk_Cor_Seq_1_Mask, Clk_Cor_Seq_2_Mask
125
CLK_COR_SEQ_LEN Attributes
125
Determining Correct CLK_COR_MIN_LAT and CLK_COR_MAX_LAT
126
Channel Bonding
127
Cccb_Arbitrator_Disable = False, Clock_Correction_Use = True
127
Cccb_Arbitrator_Disable = True, Clock_Correction_Use = False
127
Details
127
CCCB_ARBITRATOR_DISABLE Attribute
129
Chan_Bond_Seq_1_Mask, Chan_Bond_Seq_2_Mask
130
CHAN_BOND_SEQ_LEN, CHAN_BOND_SEQ_*_* Attributes
130
Disable Channel Bonding
130
Implementation Guidelines
130
Setting CHAN_BOND_LIMIT
130
Figure 3-20: Daisy-Chained Transceiver CHBONDI/CHBONDO Buses
131
RX Fabric Interface and Channel Bonding
132
Status and Event Bus
132
Status Indication
132
Event Indication
133
Rxbuferr
133
Txbuferr
133
Loopback
133
Digital Receiver
134
Figure 3-23: Digital Receiver Example
135
Clocking in Buffered Mode
136
Www.xilinx.com Virtex-4 Rocketio MGT User Guide UG076 (V4.1) November 2
138
Chapter 4: PMA Analog Design Considerations
139
Serial I/O Description
139
Differential Transmitter
139
Output Swing and Emphasis
139
Emphasis
140
Figure 4-3: Effect of 3-Tap Pre-Emphasis on a Pulse Signal
141
Figure 4-4: TX with Minimal Pre-Emphasis
143
Figure 4-5: RX after 36 Inches FR4 and Minimal Pre-Emphasis
144
Figure 4-6: TX with Maximal Pre-Emphasis
145
Differential Receiver
146
Clock and Data Recovery
146
Receive Equalization
147
Receiver Lock Control
147
Figure 4-8: AC Response of Continuous-Time Linear Receiver Equalizer
148
Special Analog Functions
149
Calibration for the Plls
149
Out-Of-Band (OOB) Signals
149
Powerdown
151
Rxdccouple
152
Rxpd
152
Txpd
152
Figure 5-1: 32-Bit CRC Inputs and Outputs
153
Chapter 5: Cyclic Redundancy Check (CRC)
154
Functionality
155
Figure 5-2: 64-Bit to 32-Bit Core Interface
156
Handling End-Of-Packet Residue
157
Latency and Timing
157
64-Bit Example
158
32-Bit Example
159
16-Bit Transmission, Hold CRC, and Residue of 8-Bit Example
160
Implementation
161
Www.xilinx.com Virtex-4 Rocketio MGT User Guide UG076 (V4.1) November 2
162
Chapter 6: Analog and Board Design Considerations
163
Physical Requirements
163
Power Conditioning
163
Figure 6-1: MGT Tile Power and Serial I/O Pins
164
Determining Power Supply Budget
165
Power Supply Requirements
165
Voltage Regulation
166
Figure 6-4: Power Filtering Network for One MGT Tile
167
Powering Unused Mgts
168
Figure 6-6: Optimizing Filtering for an MGT Column
169
Reference Clock
170
Termination
171
AC and DC Coupling
172
Figure 6-11: AC-Coupled Serial Link
173
Selectio-To-MGT Crosstalk
174
High-Speed Serial Trace Design
176
Routing Serial Traces
176
Differential Trace Design
177
Figure 6-15: Obstacle Route Geometry
178
Figure 6-16: Microstrip Edge-Coupled Differential Pair
178
Figure 6-17: Stripline Edge-Coupled Differential Pair
178
Chapter 7: Simulation and Implementation
179
Model Considerations
179
Simulation Models
179
Smartmodels
179
Hspice
180
Smartmodel Simulation Considerations
180
After Reset or Power-Up
180
Reference Clock Period Restriction
180
Reset after Changing Clock Attributes
180
RXP/RXN Period Restrictions
180
1-Byte or 2-Byte Fabric Interface Width
181
Crc
181
Loopback
181
Out-Of-Band (OOB) Signaling
181
Toggling GSR
181
Simulating in Verilog
182
Simulating in VHDL
182
8B/10B Encoding/Decoding
184
Frequency Calibration and Detector
184
Phase-Locked Loop
184
Sonet
184
MGT Ports that Cannot be Simulated
185
Txbufferr
185
Transceiver Location and Package Pin Relation
186
MGT Package Pins
186
Chapter 8: Low-Latency Design
191
Introduction
191
PCS Clocking Domains and Data Paths
192
Receiver
192
Figure 8-2: Pcs Transmit Clocking Domains and Data Paths
193
Transmitter
193
PCS Data Path Latency
194
Ports and Attributes
196
Receiver
196
Transmitter
197
Synchronizing the PMA/PCS Clocks in Low-Latency Modes
197
Transmit Latency and Output Skew
198
Clocking
198
Overview
198
TX Low-Latency Buffered Mode Without Channel Deskew
198
Www.xilinx.com Virtex-4 Rocketio MGT User Guide UG076 (V4.1) November 2
198
Reset
199
Skew
199
Use Models
199
Clocking
200
Overview
200
TX Low Latency Buffered Mode with Channel Deskew
200
Use Models
201
Figure 8-4: TX Low Latency Buffered Mode: Use Models TX_1A, TX_2A
202
Figure 8-5: TX Low Latency Buffered Mode: Use Models TX_1B, TX_2B
203
Figure 8-6: TX Low Latency Buffered Mode: Use Models TX_1C, TX_2C
204
Figure 8-7: TX Low Latency Buffered Mode: Use Models TX_1D, TX_2D
205
Figure 8-8: TX Low Latency Buffered Mode: Use Model TX_2E
206
Figure 8-9: TX Low Latency Buffered Mode: Use Model TX_2F
207
Figure 8-10: TX Low Latency Buffered Mode: Use Model TX_2G
208
Figure 8-11: Tx Low Latency Buffered Mode: Use Model Tx_2H
209
Reset
209
Skew
209
Clocking
210
Overview
210
TX Low Latency Buffer Bypass Mode
210
Use Models
211
Figure 8-13: TX Low Latency Buffer Bypass Mode: Use Model TX_3A
212
Reset
213
Skew
213
Txsync
213
Overview
213
Timing
214
Usage
214
TX Channel Skew Using TXSYNC
215
Synchronization Clock = PCS TXCLK, TXPHASESEL = TRUE
215
Worst-Case TX Skew Estimation
215
Synchronization Clock = GREFCLK, TXPHASESEL = FALSE
216
1.25 Gbit/S, Synchronization Clock = GREFCLK, TXPHASESEL = FALSE
217
1.25 Gbit/S, Synchronization Clock = PCS TXCLK, TXPHASESEL = TRUE
217
TX Skew Estimation Examples
217
RX Latency
219
Clocking
219
Overview
219
RX Low Latency Buffered Mode
219
Use Models
220
Figure 8-16: RX Low Latency Buffered Mode: Use Model RX_1A
221
Figure 8-17: RX Low Latency Buffered Mode: Use Model RX_1B
222
Figure 8-18: Rx Low Latency Buffered Mode: Use Model Rx_1C
223
Reset
223
Clocking
224
Overview
224
RX Low Latency Buffer Bypass Mode
224
Figure 8-19: RX Low Latency Buffer Bypass Mode: Use Model RX_2A
225
Figure 8-20: RX Low Latency Buffer Bypass Mode: Use Model RX_2B
226
Reset
227
Rxsync
228
Overview
228
Timing
228
Usage
228
Restrictions on Low Latency Buffer Bypass Modes
229
Example of a Reduced-Latency System
230
System Characteristics
230
Xaui
230
Board Level Design
233
Chapter 9: Methodology Overview
235
Introduction
235
Powering the Rocketio Mgts
236
Filtering
236
Regulators
236
Reference Clock
236
Clock Sources
236
Clock Traces
237
Coupling
237
AC Coupling
237
DC Coupling
237
External Capacitor Value Selection
237
Chapter 10: PCB Materials and Traces
239
How Fast Is Fast
239
PCB Losses
239
Choosing the Substrate Material
240
Loss Tangent
240
Relative Permittivity
240
Skin Effect and Resistive Losses
240
Traces
241
Trace Characteristic Impedance Design
241
Trace Geometry
241
Figure 10-1: Differential Edge-Coupled Centered Stripline
242
Plane Splits
243
Simulating Lossy Transmission Lines
243
Trace Routing
243
Cable
244
Connectors
244
Optimal Cable Length
244
Skew between Conductors
244
Chapter 11: Design of Transitions
245
Excess Capacitance and Inductance
245
Time Domain Reflectometry (TDR)
245
Figure 11-1: TDR Signature of Shunt Capacitance
246
Figure 11-4: 2D Field Solver Analysis of 5 Mil Trace and 28 Mil Pad
247
SMT Pads
247
Figure 11-6: Ansoft HFSS Model of Capacitor with a Pad Clear-Out
248
On Log (Frequency) Scale
249
Differential Vias
250
Figure 11-11: Differential GSSG Via in 16-Layer PCB from Pins L11 and L6
251
Microstrip/Stripline Bends
252
Figure 11-14: Simulated TDR of 45 Degree Bends with Jog-Outs
253
Figure 11-16: Simulated Phase Response of 45 Degree Bends with Jog-Outs
254
BGA Packages
255
SMA Connectors
255
Www.xilinx.com Virtex-4 Rocketio MGT User Guide UG076 (V4.1) November 2
256
Chapter 12: Guidelines and Examples
257
Summary of Guidelines
257
Figure 12-1: Differential Via Dimensions
258
Channel Budgeting Considerations
258
Figure 12-2: BGA Escape Design Example
261
BGA Escape Example
261
Figure 12-3: Via Structures for BGA Adjacent SIO
262
SMT XENPAK70 Connector Design Example
262
Figure 12-4: XENPAK70 Connector Design Example
263
SMT XFP Connector Design Example
263
Figure 12-5: SMT XFP Connector Design Example
264
Tyco Z-PACK HM-Zd Connector Design Example
264
Figure 12-7: Tyco Z-PACK HM-Zd Press-Fit Connector
265
Figure 12-9: Tyco Z-PACK HM-Zd Press-Fit Connector Design Example
266
SMT DC Blocking Capacitor Design Example
267
Www.xilinx.com Virtex-4 Rocketio MGT User Guide UG076 (V4.1) November 2
268
Appendixes
269
Appendix A: Rocketio Transceiver Timing Model
271
Figure A-1: Rocketio Multi-Gigabit Transceiver Block Diagram
273
Timing Parameters
274
Clock Pulse Width
274
Clock to Output Delays
274
Input Setup/Hold Times Relative to Clock
274
Figure A-2: MGT Timing Relative to Clock Edge
275
Timing Diagram and Timing Parameter Tables
275
Valid Data and Control Characters
283
Appendix B: 8B/10B Valid Characters
284
Appendix C: Dynamic Reconfiguration Port
293
Interface Description
293
Memory Map
294
Appendix D: Special Analog Functions
321
Receiver Sample Phase Adjustment
321
Appendix E: Virtex-II Pro/Virtex-II Pro X to Virtex-4 Rocketio
325
Introduction
325
Primary Differences
325
Mgts Per Device
325
Clocking
326
Encoding Support and Clock Multipliers
327
Flexibility
327
Serial Rate Support
327
Board Guidelines
328
Power Supply Filtering
328
Other Minor Differences
329
Termination
329
Crc
330
Loopback
330
Serialization
330
RXSTATUS Bus
331
Pre-Emphasis, Differential Swing, and Equalization
331
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Xilinx Virtex-4 RocketIO User Manual (176 pages)
FPGA Embedded Tri-Mode Ethernet MAC
Brand:
Xilinx
| Category:
IP Access Controllers
| Size: 3.99 MB
Table of Contents
Table of Contents
9
Preface: about this Guide
13
Guide Contents
13
Additional Resources
13
Conventions
14
Typographical
14
Online Document
14
Chapter 1: Introduction
15
Ethernet MAC Overview
15
Features
16
Chapter 2: Ethernet MAC Architecture
17
Architecture Overview
17
Ethernet MAC Primitive
20
Ethernet MAC Signal Descriptions
22
Client Signals
22
Clock Signals
25
Host Interface Signals
26
Reset and CLIENTEMAC#DCMLOCKED Signals
27
Tie-Off Pins
28
Management Data Input/Output (MDIO) Interface Signals
32
Mode-Dependent Signals
32
Rocketio Multi-Gigabit Transceiver Signals
34
Chapter 3 : Client, Host, and MDIO Interfaces
37
Client Interface
37
Transmit (TX) Client - 8-Bit Wide Interface
40
Transmit (TX) Client - 16-Bit Wide Interface
47
Receive (RX) Client - 8-Bit Wide Interface
51
Receive (RX) Client - 16-Bit Wide Interface
56
Address Filtering
58
Flow Control Block
61
Statistics Vector
65
Host Interface
72
Host Clock Frequency
74
Configuration Registers
74
Address Filter Registers
80
Using the DCR Bus as the Host Bus
83
Description of Ethernet MAC Register Access through the DCR Bus
89
Address Code
91
MDIO Interface
93
Introduction to MDIO
93
MDIO Implementation in the EMAC
95
Accessing MDIO Via the EMAC Host Interface
97
Chapter 4: Physical Interface
99
Media Independent Interface (MII)
99
MII Interface
99
MII Clock Management
101
MII Signals
104
Gigabit Media Independent Interface (GMII) Signals
105
GMII Interface
105
GMII Clock Management
107
Tri-Mode Operation with Byte PHY Enabled (Full-Duplex Only)
110
GMII Signals
112
10/100/1000 Rgmii
113
Gb/S RGMII Interface
113
Gb/S RGMII Clock Management
115
Tri-Mode RGMII V2.0
117
Tri-Mode RGMII V1.3
120
RGMII Signals
122
10/100/1000 Serial Gigabit Media Independent Interface (SGMII)
123
SGMII RX Elastic Buffer
123
10/100/1000 SGMII Interface
130
10/100/1000 SGMII Clock Management
131
SGMII Signals
132
Management Registers
134
1000Base-X Pcs/Pma
135
1000BASE-X PCS/PMA Interface
135
Shim
137
1000BASE-X PCS/PMA Clock Management
137
PCS/PMA Signals
140
Management Registers
140
Chapter 5: Miscellaneous Functions
147
Clock Frequency Support
147
Transmit Clocking Scheme
148
Receive Clocking Scheme
149
Ethernet MAC Configuration
149
Auto-Negotiation Interrupt
151
Overview of Operation
151
Auto-Negotiation Link Timer
153
Using the Auto-Negotiation Interrupt
153
Chapter 6: Use Models
155
Simulation Models
155
Secureip Model
155
Model Considerations
155
Pinout Guidelines
156
Interfacing to the Processor DCR
157
Interfacing to an FPGA Fabric-Based Statistics Block
161
When the Ethernet MAC Is Implemented with the Host Bus
161
When the Ethernet MAC Is Implemented with the DCR Bus
163
Chapter 7: Using the Embedded Ethernet MAC
167
Accessing the Ethernet MAC from the CORE Generator Tool
167
Simulating the Ethernet MAC Using the Ethernet MAC Wrappers
167
Appendix A: Ethernet MAC Timing Model
169
Timing Parameters
169
Input Setup/Hold Times Relative to Clock
169
Clock to Output Delays
170
Core Latency
170
Timing Diagram and Timing Parameter Tables
171
Xilinx Virtex-4 RocketIO Configuration User Manual (114 pages)
FPGA
Brand:
Xilinx
| Category:
Motherboard
| Size: 1.47 MB
Table of Contents
Revision History
2
Table of Contents
5
Preface: about this Guide
9
Guide Contents
9
Additional Documentation
9
Additional Resources
10
Typographical Conventions
10
Online Document
11
Chapter 1: Configuration Overview
13
Introduction
13
Setup (Steps 1-3)
15
Device Power-Up (Step 1)
15
Clear Configuration Memory (Step 2, Initialization)
16
Sample Mode Pins (Step 3)
17
Delaying Configuration
17
Bitstream Loading (Steps 4-7)
18
Synchronization (Step 4)
18
Check Device ID (Step 5)
19
Load Configuration Data Frames (Step 6)
20
Cyclic Redundancy Check (Step 7)
20
Startup (Step 8)
21
Bitstream Encryption
23
AES Overview
23
Creating an Encrypted Bitstream
24
Loading the Encryption Key
24
Loading Encrypted Bitstreams
24
Bitstream Encryption and Internal Configuration Access Port (ICAP)
25
Vbatt
25
Chapter 2: Configuration Interfaces
27
Serial Configuration Interface
27
Clocking Serial Configuration Data
29
Master Serial Configuration
29
Slave Serial Configuration
30
Serial Daisy Chains
30
Configuring a Serial Daisy Chain with a Microprocessor or CPLD
32
Mixed Serial Daisy Chains
33
Guidelines and Design Considerations for Serial Daisy Chains
33
Ganged Serial Configuration
37
Startup Sequencing (GTS)
38
Disable the Active DONE Driver on for All Devices
38
Connect All DONE Pins if Using a Master Device
38
DONE Pin Rise Time
38
Configuration Clock (CCLK) as Clock Signal for Board Layout
38
Signal Fanout
38
PROM Files for Ganged Serial Configuration
39
Selectmap Configuration Interface
39
Single Device Selectmap Configuration
41
Multiple Device Selectmap Configuration
42
Ganged Selectmap
44
Selectmap Data Loading
45
Continuous Selectmap Data Loading
46
Non-Continuous Selectmap Data Loading
48
Selectmap ABORT
49
Configuration Abort Sequence Description
49
Readback Abort Sequence Description
50
ABORT Status Word
50
Resuming Configuration or Readback after an Abort
51
Selectmap Reconfiguration
51
Selectmap Data Ordering
52
Configuration Data Files
53
Byte Swapping
53
Generating PROM Files
54
PROM Files for Serial Daisy Chains
54
PROM Files for Selectmap Configuration
55
Chapter 3: Boundary-Scan and JTAG Configuration
57
Introduction
57
Boundary-Scan for Virtex-4 Devices Using IEEE Standard 1149.1
57
Test Access Port
57
TAP Controller
59
Boundary-Scan Architecture
61
Boundary-Scan Register
61
Instruction Register
62
BYPASS Register
64
Identification Register
64
Configuration Register (Boundary-Scan)
66
USERCODE Register
66
USER1, USER2, USER3, and USER4 Registers
66
Using Boundary-Scan in Virtex-4 Devices
66
Configuring through Boundary-Scan
67
Reconfiguring through Boundary-Scan
70
Boundary-Scan for Virtex-4 Devices Using IEEE Standard 1532
71
ISC Modal States
71
Clocking Startup and Shutdown Sequences (JTAG)
72
Configuration Flows Using JTAG
73
Chapter 4: Frame ECC Logic
75
Using Frame ECC Logic
75
Chapter 5: User Access Register
77
Using the User Access Register
77
Chapter 6: Reconfiguration Techniques
79
Dynamic Reconfiguration of Functional Blocks (DRP)
79
Background
79
Overview
79
FPGA Fabric Port Definition
80
DRP DCM Implementation
83
Changing the Multiply and Divide Values
83
Dynamic Phase Shifting through the DRP in Direct Mode
84
ICAP - Internal Configuration Access Port
85
Chapter 7 : Configuration Details
87
Configuration Memory Frames
87
Configuration Control Logic
88
Packet Types
88
Type 1 Packet
88
Type 2 Packet
89
Configuration Registers
89
Command Register (CMD)
90
Control Register (CTL)
91
Frame Address Register (FAR)
92
Status Register (STAT)
93
Configuration Options Register (COR)
94
Bitstream Composition
96
Default Initial Configuration Process
96
Chapter 8: Readback and Configuration Verification
99
Preparing a Design for Readback
99
Readback Command Sequences
100
Accessing Configuration Registers through the Selectmap Interface
100
Configuration Register Read Procedure (Selectmap)
101
Configuration Memory Read Procedure (Selectmap)
102
Accessing Configuration Registers through the JTAG Interface
104
Configuration Register Read Procedure - JTAG
104
Configuration Memory Read Procedure (1149.1 JTAG)
106
Configuration Memory Read Procedure (1532 JTAG)
109
Verifying Readback Data
110
Readback Capture
113
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