Xilinx Virtex-6 Manual page 39

WIDTH_PREADD => 25,
WIDTH_MULTIPLIER => 18, -- Multiplier input bus width, 1-18
WIDTH_PRODUCT => 48)
port map (
PRODUCT => PRODUCT,
MULTIPLIER => MULTIPLIER, -- Multiplier data input, width determined by WIDTH_MULTIPLIER generic
PREADDER1 => PREADDER1,
PREADDER2 => PREADDER2,
CARRYIN => CARRYIN, -- 1-bit carry-in input
CE => CE, -- 1-bit input clock enable
CLK => CLK, -- 1-bit clock input
LOAD => LOAD, -- 1-bit accumulator load input
LOAD_DATA => LOAD_DATA, -- Accumulator load data input, width defined by WIDTH_PRODUCT generic
RST => RST -- 1-bit input active high synchronous reset
);
-- End of ADDMACC_MACRO_inst instantiation
Verilog Instantiation Template
// ADDMACC_MACRO: Variable width & latency - Pre-Add -> Multiplier -> Accumulate
// function implemented in a DSP48E
// Virtex-6
// Xilinx HDL Libraries Guide, version 14.5
ADDMACC_MACRO #(
.DEVICE("VIRTEX6"),
.LATENCY(4),
.WIDTH_PREADD(25),
.WIDTH_MULTIPLIER(18), // Multiplier input width, 1-18
.WIDTH_PRODUCT(48)
) ADDMACC_MACRO_inst (
.PRODUCT(PRODUCT),
.CARRYIN(CARRYIN),
.CLK(CLK),
.CE(CE),
.LOAD(LOAD),
.LOAD_DATA(LOAD_DATA),
.MULTIPLIER(MULTIPLIER), // Multiplier data input, width defined by WIDTH_MULTIPLIER parameter
.PREADD2(PREADD2),
.PREADD1(PREADD1),
.RST(RST)
);
// End of ADDMACC_MACRO_inst instantiation
For More Information
See the Virtex-6 FPGA User Documentation (User Guides and Data
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
-- Pre-Adder input bus width, 1-25
-- MACC output width, 1-48
-- MACC result output, width defined by WIDTH_PRODUCT generic
-- Preadder data input, width determined by WIDTH_PREADDER generic
-- Preadder data input, width determined by WIDTH_PREADDER generic
// Target Device: "VIRTEX6", "SPARTAN6"
// Desired clock cycle latency, 0-4
// Pre-adder input width, 1-25
// MACC output width, 1-48
// MACC result output, width defined by WIDTH_PRODUCT parameter
// 1-bit carry-in input
// 1-bit clock input
// 1-bit clock enable input
// 1-bit accumulator load input
// Accumulator load data input, width defined by WIDTH_PRODUCT parameter
// Preadder data input, width defined by WIDTH_PREADD parameter
// Preadder data input, width defined by WIDTH_PREADD parameter
// 1-bit active high synchronous reset
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Chapter 2: About Unimacros
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