Xilinx Virtex-6 Manual page 127

FDRE
Primitive: D Flip-Flop with Clock Enable and Synchronous Reset
Introduction
This design element is a single D-type flip-flop with data (D), clock enable (CE), and synchronous reset (R) inputs
and data output (Q). The synchronous reset (R) input, when High, overrides all other inputs and resets the (Q)
output Low on the Low-to-High clock (C) transition. The data on the (D) input is loaded into the flip-flop when R
is Low and CE is High during the Low-to-High clock transition.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-on
conditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted
by adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic Table
Inputs
R CE
1 X
0 0
0 1
Design Entry Method
Instantiation
Inference
CORE Generator™ and wizards
Macro support
Available Attributes
Data
Attribute Type
INIT Binary
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
D
X
X
D
Allowed Values Default
0, 1 0
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Chapter 4: About Design Elements
C
↑
X
↑
Yes
Recommended
No
No
Description
Sets the initial value of Q output after
configuration
Outputs
Q
0
No Change
D
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