Chapter 2: About Unimacros
.RST(RST)
// 1-bit input active high reset
);
// End of MULT_MACRO_inst instantiation
For More Information
See the
Virtex-6 FPGA User Documentation (User Guides and Data
Sheets).
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
www.xilinx.com
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