Xilinx Virtex-6 Manual page 57

Hide thumbs Also See for Virtex-6:
Table of Contents

Advertisement

Chapter 2: About Unimacros
.RST(RST)
// 1-bit input active high reset
);
// End of MULT_MACRO_inst instantiation
For More Information
See the
Virtex-6 FPGA User Documentation (User Guides and Data
Sheets).
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
www.xilinx.com
57

Advertisement

Table of Contents
loading

Table of Contents