Xilinx Virtex-6 Manual page 328

Chapter 4: About Design Elements
Data
Attribute Type
READ_WIDTH_B Integer
RSTREG_PRIORITY_A String
RSTREG_PRIORITY_B String
SRVAL_A Hexa-
decimal
SRVAL_B Hexa-
decimal
WRITEMODE String
WRITE_WIDTH_A Integer
Integer
WRITE_WIDTH_B
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
328
Allowed Values Default
0, 1, 2, 4, 9, 18 0
"RSTREG", "RSTREG"
"REGCE"
"RSTREG", "RSTREG"
"REGCE"
Any 18 Bit Value All zeros
Any 18 Bit Value All zeros
"WRITE_FIRST", "WRITE_
"READ_FIRST" FIRST"
"NO_CHANGE"
0, 1, 2, 4, 9, 18 0
0, 1, 2, 4, 9, 18, 36, 72 0
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Description
Specifies the desired data width for a
read on Port B including parity bits.
This value must be 0 if the Port B is not
used. Otherwise, it should be set to
the desired port width. Not used for
SDP mode.
Selects register priority for RSTREG
or REGCE. Applies to port A in
TDP mode and up to 18 lower bits
(including parity bits) in SDP mode.
Selects register priority for RSTREG
or REGCE. Applies to port B in TDP
mode and upper bits (including parity
bits) in SDP mode.
Specifies the output value of the RAM
upon assertion of the synchronous
reset (RSTREG) signal. Applies to port
A in TDP mode and up to 18 lower bits
(including parity bits) in SDP mode.
Specifies the output value of the RAM
upon assertion of the synchronous
reset (RSTREG) signal. Applies to
port B in TDP mode and upper bits
(including parity bits) in SDP mode.
Specifies output behavior of the port
being written to:
• "WRITE_FIRST" - written value
appears on output port of the
RAM
• "READ_FIRST" - previous RAM
contents for that memory location
appear on the output port
• "NO_CHANGE" - previous value
on the output port remains the
same.
Specifies the desired data width for a
write to Port A including parity bits.
This value must be 0 if the port is not
used. Otherwise should be set to the
desired write width. Not used in SDP
mode.
Specifies the desired data width for a
write to Port B including parity bits.
This value must be 0 if the port is not
used. Otherwise should be set to the
desired write width. In SDP mode, this
is the write width including parity bits.
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013