Xilinx Virtex-6 Manual page 236

Chapter 4: About Design Elements
LUT6_2
Primitive: Six-input, 2-output, Look-Up Table
Introduction
This design element is a 6-input, 2-output look-up table (LUT) that can either act as a dual asynchronous 32-bit
ROM (with 5-bit addressing), implement any two 5-input logic functions with shared inputs, or implement a
6-input logic function and a 5-input logic function with shared inputs and shared logic values. LUTs are the
basic logic building blocks and are used to implement most logic functions of the design. A LUT6_2 will be
mapped to one of the four look-up tables in the slice.
An INIT attribute consisting of a 64-bit hexadecimal value must be specified to indicate the LUTs logical function.
The INIT value is calculated by assigning a 1 to corresponding INIT bit value when the associated inputs are
applied. For instance, a Verilog INIT value of 64'hfffffffffffffffe (X"FFFFFFFFFFFFFFFE" for VHDL) makes the O6
output 1 unless all zeros are on the inputs and the O5 output a 1, or unless I[4:0] are all zeroes (a 5-input and
6-input OR gate). The lower half (bits 31:0) of the INIT values apply to the logic function of the O5 output.
The INIT parameter for the FPGA LUT primitive is what gives the LUT its logical value. By default, this value is
zero, thus driving the output to a zero regardless of the input values (acting as a ground). However, in most
cases a new INIT value must be determined in order to specify the logic function for the LUT primitive. There
are at least two methods by which the LUT value can be determined:
• The Logic Table Method -A common method to determine the desired INIT value for a LUT is using a logic
table. To do so, simply create a binary logic table of all possible inputs, specify the desired logic value of
the output and then create the INIT string from those output values.
• The Equation Method -Another method to determine the LUT value is to define parameters for each input
to the LUT that correspond to their listed truth value and use those to build the logic equation. This method
is easier to understand once you have grasped the concept and is more self-documenting than the above
method. However, this method does require the code to first specify the appropriate parameters.
Logic Table
Inputs
I5 I4 I3
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
236
I2 I1
0 0
0 0
0 1
0 1
1 0
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Outputs
I0 O5
0 INIT[0]
1 INIT[1]
0 INIT[2]
1 INIT[3]
0 INIT[4]
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
O6
INIT[0]
INIT[1]
INIT[2]
INIT[3]
INIT[4]