Xilinx Virtex-6 Manual page 181

Port
CLKDIV
D
DDLY
DYNCLKDIVSEL
DYNCLKSEL
O
OCLK
OCLKB
OFB
Q1 - Q6
RST
SHIFTIN1/
SHIFTIN2
SHIFTOUT1/
SHIFTOUT2
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Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Direction Width Function
MEMORY_QDR mode CLKB should be connected to a unique,
phase shifted clock
Input 1
Divided clock to be used for parallelized data.
Input 1
Input data to be connected directly to the top-level input or I/O
port of the design or to an IODELAY component if additional
input delay control is desired.
Input 1 Serial input from IODELAY.
Input 1 Dynamically select CLKDIV inversion.
Input 1 Dynamically select CLK and CLKB inversion.
Output 1 Combinatorial output.
Input 1 High speed output clock typically used for memory interfaces.
Input 1 Used for Async Oversampling.
Input 1 The output feedback port (OFB) is the serial (high-speed) data
output port of the OSERDESE1 or the bypassed version of the
CLKPERF. When the attribute ODELAYUSED is set to 0, the OFB
port can be used to send out serial data to the ISERDESE1. When
the attribute ODELAYUSED is set to 1 and the OSERDESE1 is in
MEMORY_DDR3 mode, the OFB port can be used to link the
high-performance clock input (CLKPERF) to the IODELAYE1.
1
Output The output ports Q1 to Q6 are the registered outputs of the
ISERDESE1 module. One ISERDESE1 block can support up to
six bits (i.e., a 1:6 deserialization). Bit widths greater than six (up
to 10) can be supported.
Input 1
Active High asynchronous reset signal for the registers of the
SERDES.
Input 1 If ISERDES_MODE="SLAVE" connect to the master
ISERDES_NODELAY IDATASHIFTOUT1/2 outputs. This pin
must be grounded.
Output 1
If ISERDES_MODE="MASTER" and two ISERDES_NODELAY
are to be cascaded, connect to the slave ISERDES_NODELAY
IDATASHIFTIN1/2 inputs.
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Chapter 4: About Design Elements
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