Xilinx Virtex-6 Manual page 158

Chapter 4: About Design Elements
Available Attributes
Data
Attribute Type
IOSTANDARD String
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- IBUFGDS: Differential Global Clock Input Buffer
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
IBUFGDS_inst : IBUFGDS
generic map (
DIFF_TERM => FALSE, -- Differential Termination
IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT")
port map (
O => O, -- Clock buffer output
I => I, -- Diff_p clock buffer input (connect directly to top-level port)
IB => IB -- Diff_n clock buffer input (connect directly to top-level port)
);
-- End of IBUFGDS_inst instantiation
Verilog Instantiation Template
// IBUFGDS: Differential Global Clock Input Buffer
// Virtex-6
// Xilinx HDL Libraries Guide, version 14.5
IBUFGDS #(
.DIFF_TERM("FALSE"),
.IOSTANDARD("DEFAULT")
) IBUFGDS_inst (
.O(O), // Clock buffer output
.I(I), // Diff_p clock buffer input (connect directly to top-level port)
.IB(IB) // Diff_n clock buffer input (connect directly to top-level port)
);
// End of IBUFGDS_inst instantiation
For More Information
See the Virtex-6 FPGA User Documentation (User Guides and Data
158
Allowed
Values Default
See Data Sheet "DEFAULT"
// Differential Termination
// Specify the input I/O standard
www.xilinx.com
Description
Assigns an I/O standard to the
element.
Sheets).
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013