Xilinx Virtex-6 Manual page 114

Chapter 4: About Design Elements
Port
CEB1
CEB2
CEC
CECARRYIN
CECTRL
CED
CEINMODE
CEM
CEP
CLK
D[24:0]
INMODE[4:0]
MULTSIGNIN
MULTSIGNOUT
OPMODE[6:0]
OVERFLOW
P[47:0]
PATTERNBDETECT
PATTERNDETECT
114
Direction Width Function
Input 1 Active high, clock enable for the first B (input) register. This port
is only used if BREG = 2 or INMODE0 = 1. Tie to logic one if not
used and BREG=2. When two registers are used, this is the first
sequentially. When Dynamic AB Access is used, this clock enable is
applied for INMODE[0]=1. If B/BCIN port is not used, BREG should
be set to 1 and CEB1 tied to 0.
Input 1 Active High, clock enable for the B port registers. Tie to logic one if
not used and BREG=1 or 2. Tie to logic zero if BREG=0. When two
registers are used, this is the second sequentially.
Input 1 Active High, clock enable for the C port registers (CREG=1). If C
port is not used, CREG should be set to 1 and CEC tied to logic 0.
Input 1 Active High, clock enable for the carry-in registers
(CARRYINREG=1). If CARRYIN=0, CARRYINREG should be tied to
logic 0.
Input 1 Active High, clock enable for the OPMODE and CARRYINSEL
registers. If OPMODEREG=0, CARRYINSELREG should be tied to
logic 0.
Input 1
Active High, clock enable for the D port registers (DREG=1). If D
port is not used, DREG should be set to 1 and CED tied to logic 0.
Input 1 Active High, clock enable for the INMODE input registers
(INMODEREG=1). If INMODE=0, CARRYINREG should be tied to
logic 0.
Input 1 Active High, clock enable for the multiplier registers (MREG=1). If
MREG=0, CEM should be tied to logic 0.
Input 1 Active High, clock enable for the output port registers (PREG=1). If
PREG=0, PEM should be tied to logic 0.
Input 1
DSP slice clock input.
Input 25
25-bit data input to the Pre-adder or alternative input to the
Multiplier. Tie port to all ones if not used.
Input 5 Control input to select the arithmetic operation of the DSP slice
in conjunction with ALUMODE and OPMODE. INMODE signals
control the functionality of the signals and blocks that precede the
Multiplier (including the pre-adder).
Input 1 Multiplier sign input from upstream cascaded DSP slice. Use for the
purpose of sign extending the MACC output when greater than
48-bit output. Should only be connected to the MULTSIGNOUT
output pin.
Output 1 Multiplier sign output sent to downstream cascaded DSP slice. Use
for the purpose of sign extending the MACC output when greater
than 48-bit output. Should only be connected to the MULTISIGNIN
input pin.
Input 7
Control input to select the arithmetic operation of the DSP slice in
conjunction with ALUMODE and INMODE.
Output 1
Active High output detects overflow in addition/accumulate if
pattern detector is used and PREG=1.
Output 48 Primary data output.
Output 1 Active High pattern detection. Detects match of P and the bar of the
selected PATTERN gated by the MASK. Result arrives on the same
cycle as P.
Output 1
Active High pattern detection. Detects match of P and the selected
PATTERN gated by the MASK. Result arrives on the same cycle as P.
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Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013