Xilinx Virtex-6 Manual page 44

Chapter 2: About Unimacros
Instantiation
Inference
CORE Generator™ and wizards
Macro support
Available Attributes
Attribute Data Type
DEVICE String
COUNT_BY Hexa-
decimal
WIDTH_DATA Integer
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- COUNTER_LOAD_MACRO: Loadable variable counter implemented in a DSP48E
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
COUNTER_LOAD_MACRO_inst : COUNTER_LOAD_MACRO
generic map (
COUNT_BY => X"000000000001", -- Count by value
DEVICE => "VIRTEX6",
WIDTH_DATA => 48)
port map (
Q => Q,
CLK => CLK,
CE => CE,
DIRECTION => DIRECTION, -- 1-bit up/down count direction input, high is count up
LOAD => LOAD,
LOAD_DATA => LOAD_DATA, -- Counter load data, width determined by WIDTH_DATA generic
RST => RST
);
-- End of COUNTER_LOAD_MACRO_inst instantiation
Verilog Instantiation Template
// COUNTER_LOAD_MACRO: Loadable variable counter implemented in a DSP48E
// Virtex-6
// Xilinx HDL Libraries Guide, version 14.5
COUNTER_LOAD_MACRO #(
.COUNT_BY(48'h000000000001), // Count by value
.DEVICE("VIRTEX6"), // Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6"
.WIDTH_DATA(48) // Counter output bus width, 1-48
) COUNTER_LOAD_MACRO_inst (
.Q(Q),
.CLK(CLK),
.CE(CE),
.DIRECTION(DIRECTION), // 1-bit up/down count direction input, high is count up
.LOAD(LOAD),
.LOAD_DATA(LOAD_DATA), // Counter load data, width determined by WIDTH_DATA parameter
.RST(RST)
);
44
Allowed Values
"VIRTEX6",
"SPARTAN6"
Any 48 bit value.
1-48
-- Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6"
-- Counter output bus width, 1-48
-- Counter output, width determined by WIDTH_DATA generic
-- 1-bit clock input
-- 1-bit clock enable input
-- 1-bit active high load input
-- 1-bit active high synchronous reset
// Counter output, width determined by WIDTH_DATA parameter
// 1-bit clock input
// 1-bit clock enable input
// 1-bit active high load input
// 1-bit active high synchronous reset
www.xilinx.com
Yes
No
No
Recommended
Default Description
"VIRTEX6" Target hardware architecture.
000000000001 Count by n; takes precedence over
WIDTH_DATA.
48 Specifies counter width.
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013