Xilinx Virtex-6 Manual page 292

Chapter 4: About Design Elements
Verilog Instantiation Template
// PULLDOWN: I/O Buffer Weak Pull-down
// Virtex-6
// Xilinx HDL Libraries Guide, version 14.5
PULLDOWN PULLDOWN_inst (
.O(O) // Pulldown output (connect directly to top-level port)
);
// End of PULLDOWN_inst instantiation
For More Information
See the Virtex-6 FPGA User Documentation (User Guides and Data
292
Sheets).
Virtex-6 Libraries Guide for HDL Designs
www.xilinx.com UG623 (v 14.5) March 20, 2013