Xilinx Virtex-6 Manual page 137

Available Attributes
Attribute
ALMOST_EMPTY_
OFFSET
ALMOST_FULL_
OFFSET
DATA_WIDTH
DO_REG
EN_ECC_READ
EN_ECC_WRITE
EN_SYN
FIFO_MODE
FIRST_WORD_FALL_
THROUGH
INIT
SRVAL
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- FIFO36E1: 36KB FIFO (First In, First Out) Block RAM Memory
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
FIFO36E1_inst : FIFO36E1
generic map (
ALMOST_EMPTY_OFFSET => X"0080",
ALMOST_FULL_OFFSET => X"0080",
DATA_WIDTH => 4,
DO_REG => 1,
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
EN_SYN => FALSE,
FIFO_MODE => "FIFO36",
FIRST_WORD_FALL_THROUGH => FALSE, -- Sets the FIFO FWFT to TRUE or FALSE
INIT => X"000000000000000000",
SRVAL => X"000000000000000000"
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Data Type Allowed Values
Hexa-
13'h0000 to 13'h8191
decimal
Hexa- 13'h0000 to 13'h8191
decimal
Integer 4, 9, 18, 36, 72
Integer 1, 0
Boolean FALSE, TRUE
Boolean FALSE, TRUE
Boolean FALSE, TRUE
String "FIFO36,
"FIFO36_72"
Boolean FALSE, TRUE
Hexa- Any 72 bit Value
decimal
Hexa-
Any 72 bit Value
decimal
-- Sets the almost empty threshold
-- Sets almost full threshold
-- Sets data width to 4, 9, 18, 36, or 72
-- Enable output register (0 or 1) Must be 1 if EN_SYN = FALSE
-- Enable ECC decoder, TRUE or FALSE
-- Enable ECC encoder, TRUE or FALSE
-- Specifies FIFO as Asynchronous (FALSE) or Synchronous (TRUE)
-- Sets mode to FIFO36 or FIFO36_72
-- Initial values on output port
-- Set/Reset value for output port
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Chapter 4: About Design Elements
Default Description
13'h0080 Specifies the amount of data
contents in the RAM to trigger the
ALMOST_EMPTY flag.
13'h0080 Specifies the amount of data
contents in the RAM to trigger the
ALMOST_FULL flag.
4 Specifies the desired data width for
the FIFO.
1
Enable output register to the FIFO for
improved clock-to-out timing at the
expense of added read latency (one
pipeline delay). DO_REG must be 1
when EN_SYN is set to FALSE.
FALSE Enable the ECC decoder circuitry.
FALSE Enable the ECC encoder circuitry.
FALSE When FALSE, specifies the FIFO to
be used in asynchronous mode (two
independent clock). When TRUE in
synchronous (a single clock) operation.
"FIFO36" Selects FIFO36 or FIFO36_72 mode.
FALSE If TRUE, the first write to the FIFO
will appear on DO without an RDEN
assertion.
All zeros Specifies the initial value on the DO
output after configuration.
All zeros Specifies the output value of the FIFO
upon assertion of the synchronous
reset (RSTREG) signal. Only valid for
DO_REG=1.
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