Xilinx Virtex-6 Manual page 208

Chapter 4: About Design Elements
Design Entry Method
Instantiation
Inference
CORE Generator™ and wizards
Macro support
Available Attributes
Attribute Data Type
INIT
Hexadecimal
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- LUT3: 3-input Look-Up Table with general output
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
LUT3_inst : LUT3
generic map (
INIT => X"00")
port map (
O => O, -- LUT general output
I0 => I0, -- LUT input
I1 => I1, -- LUT input
I2 => I2 -- LUT input
);
-- End of LUT3_inst instantiation
Verilog Instantiation Template
// LUT3: 3-input Look-Up Table with general output
// Virtex-6
// Xilinx HDL Libraries Guide, version 14.5
LUT3 #(
.INIT(8'h00) // Specify LUT Contents
) LUT3_inst (
.O(O), // LUT general output
.I0(I0), // LUT input
.I1(I1), // LUT input
.I2(I2) // LUT input
);
// End of LUT3_inst instantiation
For More Information
See the Virtex-6 FPGA User Documentation (User Guides and Data
208
Yes
Recommended
No
No
Allowed Values Default
Any 8-Bit Value All zeros
Sheets).
www.xilinx.com
Description
Initializes look-up tables.
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013