Xilinx Virtex-6 Manual page 126

Chapter 4: About Design Elements
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- FDPE: Single Data Rate D Flip-Flop with Asynchronous Preset and
-- Clock Enable (posedge clk).
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
FDPE_inst : FDPE
generic map (
INIT => '0') -- Initial value of register ('0' or '1')
port map (
Q => Q, -- Data output
C => C, -- Clock input
CE => CE, -- Clock enable input
PRE => PRE, -- Asynchronous preset input
D => D -- Data input
);
-- End of FDPE_inst instantiation
Verilog Instantiation Template
// FDPE: Single Data Rate D Flip-Flop with Asynchronous Preset and
// Clock Enable (posedge clk).
// Virtex-6
// Xilinx HDL Libraries Guide, version 14.5
FDPE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDPE_inst (
.Q(Q), // 1-bit Data output
.C(C), // 1-bit Clock input
.CE(CE), // 1-bit Clock enable input
.PRE(PRE), // 1-bit Asynchronous preset input
.D(D) // 1-bit Data input
);
// End of FDPE_inst instantiation
For More Information
See the Virtex-6 FPGA User Documentation (User Guides and Data
126
Sheets).
Virtex-6 Libraries Guide for HDL Designs
www.xilinx.com UG623 (v 14.5) March 20, 2013