Xilinx Virtex-6 Manual page 113

Port Descriptions
Port
A[29:0]
ACIN[29:0]
ACOUT[29:0]
ALUMODE[3:0]
B[17:0]
BCIN[17:0]
BCOUT[17:0]
C[47:0]
CARRYCASCIN
CARRYCASCOUT
CARRYIN
CARRYINSEL[2:0]
CARRYOUT[3:0]
CEAD
CEALUMODE
CEA1
CEA2
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Direction Width Function
Input 30
25-bit data input to Multiplier, Pre-adder, or 30-bit MSB Data Input
to Adder/Logic Unit. Tie port to all ones if not used.
Input 30 Cascade input for Port A. If used, connect to ACOUT of upstream
cascaded DSP slice. Tie port to all zeros if not used.
30
Output Cascade output for Port A. If used, connect to ACIN of downstream
cascaded DSP slice. Leave unconnected if not used.
Input 4 Control input to select Logic Unit functions including addition and
subtraction.
Input 18 18-bit data input to Multiplier, or 18-bit LSB Data Input to
Adder/Logic Unit. Tie port to all ones if not used.
Input 18
Cascade input for Port B. If used, connect to BCOUT of upstream
cascaded DSP slice. Tie port to all zeros if not used.
Output 18 Cascade output for Port B. If used, connect to BCIN of downstream
cascaded DSP slice. Leave unconnected if not used.
Input 48 48-bit data input to Adder/Logic Unit and Pattern Detector. Tie port
to all ones if not used.
Input 1
Cascaded CARRYIN from upstream DSP slice.
Output 1
Cascaded CARRYOUT to downstream DSP slice.
Input 1
External carry input to the Adder/Logic Unit.
Input 3
Selects carry-in source to the DSP slice.
Output 4 Carry out signal for arithmetic operations (addition, subtraction,
etc.).
• If USE_SIMD="FOUR12", CARRYOUT represents the carry-out
of each 12 bit field of the Accumulate/Adder/Logic Unit.
• If USE_SIMD="TWO24" CARRYOUT and CARRYOUT represent
the carry-out of each 24-bit field of the Accumulator/Adder.
• If USE_SIMD="ONE48", CARRYOUT is the only valid carry out
from the Accumulate/Adder/Logic Unit.
Input 1
Active High, clock enable for pre-adder output AD pipeline register.
Tie to logic one if not used and ADREG=1. Tie to logic zero if
ADREG=0.
Input 1 Active High, clock enable for the ALUMODE input registers
(ALUMODEREG=1). If ALUMODEREG=0, CEALUMODE should
be tied to logic 0.
Input 1 Active high, clock enable for the first A (input) register. This port
is only used if AREG = 2 or INMODE0 = 1. Tie to logic one if not
used and AREG=2. When two registers are used, this is the first
sequentially. When Dynamic AB Access is used, this clock enable
is applied for INMODE[0]=1. If A/ACIN port is not used, AREG
should be set to 1 and CEA1 tied to 0.
Input 1 Active High, clock enable for the A port registers. Tie to logic one if
not used and AREG=1 or 2. Tie to logic zero if AREG=0. When two
registers are used, this is the second sequentially.
www.xilinx.com
Chapter 4: About Design Elements
113