Xilinx Virtex-5 RocketIO GTP Manuals

Manuals and User Guides for Xilinx Virtex-5 RocketIO GTP. We have 1 Xilinx Virtex-5 RocketIO GTP manual available for free PDF download: User Manual

Xilinx Virtex-5 RocketIO GTP User Manual (316 pages)

Brand: Xilinx | Category: Transceiver | Size: 8.14 MB

Revision History
2
Table of Contents
5
Preface: about this Guide

13
- Guide Contents
  13
- Additional Documentation
  14
- Additional Support Resources
  15
- Typographical Conventions
  15
  - Online Document
    16
Section 1: FPGA Level Design

17
- Chapter 1: Introduction to the Rocketio GTP Transceiver
  
  19
  - Overview
    19
- Chapter 2: Rocketio GTP Transceiver Wizard
  
  19
  - Ports and Attributes
    23
    
    Sim_Gtpreset_Speedup
    37
    
    Sim_Pll_Perdiv2
    37
- Chapter 3 : Simulation
  
  41
  - Overview
    41
  - Ports and Attributes
    42
  - Description
    42
    
    Limitations
    42
    
    Link Idle Reset
    43
    
    Power-Up and Reset
    43
    
    Sim_Receiver_Detect_Pass
    43
    
    Smartmodel Attributes
    43
    
    Defining GSR/GTS in a Test Bench
    44
    
    Providing Clocks in Simulation
    44
    
    Simulating in Verilog
    44
    
    Simulating in VHDL
    44
    
    Toggling GSR
    44
    
    Examples
    46
    
    Simulation Environment Setup Example (Modelsim SE 6.1D on Linux)
    46
    
    SIM_PLL_PERDIV2 Calculation Example
    46
    
    Overview
    49
    
    Ports and Attributes
    49
- Chapter 4: Implementation
  
  50
- Chapter 5: Tile Features
  
  59
  - Tile Features Overview
    59
  - Shared PMA PLL
    60
    
    Overview
    60
    
    Ports and Attributes
    60
    
    Description
    62
    
    Configuring the Shared PLL for XAUI
    64
    
    Examples
    64
    
    Configuring the Shared PLL for
    65
    
    Configuring the Shared PLL for Gigabit Ethernet
    66
    
    Configuring Shared PLL for PCI Express
    67
    
    Clocking
    68
    
    Overview
    68
    
    Clocking from an External Source
    70
    
    Description
    70
    
    Ports and Attributes
    70
    
    Clocking from a Neighbor GTP_DUAL Tile
    71
    
    Clocking Using GREFCLK
    72
    
    Overview
    72
    
    Reset
    72
    
    Ports and Attributes
    73
    
    Description
    74
    
    GTP Reset in Response to Completion of Configuration
    74
    
    GTP Component-Level Resets
    75
    
    GTP Reset When the GTPRESET Port Is Asserted
    75
    
    Link Idle Reset Support
    75
    
    Resetting the GTP_DUAL Tile
    77
    
    Examples
    79
    
    Overview
    81
    
    Ports and Attributes
    81
    
    Power Control
    81
    
    Description
    82
    
    Generic GTP Power Control Capabilities
    82
    
    Power Control Features for PCI Express
    84
    
    Examples
    85
    
    Powerdown Transition Times
    85
    
    Description
    87
    
    Dynamic Reconfiguration Port (DRP)
    87
    
    Overview
    87
    
    Ports and Attributes
    87
- Chapter 6 : GTP Transmitter (TX)
  
  89
  - Transmitter Overview
    89
  - FPGA TX Interface
    90
    
    Overview
    90
    
    Ports and Attributes
    90
    
    Configuring the Width of the Interface
    91
    
    Description
    91
    
    Connecting TXUSRCLK and TXUSRCLK2
    92
    
    Examples
    93
    
    TXOUTCLK Driving a GTP TX in 1-Byte Mode
    93
    
    TXOUTCLK Driving GTP TX in 2-Byte Mode
    94
    
    TXOUTCLK Driving Multiple Transceivers for a 2-Byte Datapath
    95
    
    REFCLKOUT Driving Multiple Transceivers with a 2-Byte Interface
    96
    
    Configurable 8B/10B Encoder
    98
    
    Overview
    98
    
    Ports and Attributes
    99
    
    8B/10B Bit and Byte Ordering
    100
    
    Description
    100
    
    Enabling 8B/10B Encoding
    100
    
    K Characters
    101
    
    Running Disparity
    101
    
    8B/10B Bypass
    102
    
    Overview
    102
    
    TX Buffering, Phase Alignment, and Buffer Bypass
    102
    
    Ports and Attributes
    104
    
    Description
    106
    
    Using the TX Buffer
    106
    
    Using the TX Phase-Alignment Circuit to Bypass the TX Buffer
    106
    
    Using the TX Phase Alignment Circuit to Minimize TX Skew
    107
    
    Description
    108
    
    Overview
    108
    
    Ports and Attributes
    108
    
    TX Polarity Control
    108
    
    Overview
    109
    
    Ports and Attributes
    109
    
    TX PRBS Generator
    109
    
    Description
    110
    
    Overview
    110
    
    Parallel in to Serial out (PISO)
    110
    
    Ports and Attributes
    110
    
    Description
    111
    
    Configurable TX Driver
    112
    
    Overview
    112
    
    Description
    113
    
    Differential Voltage Control
    113
    
    Ports and Attributes
    113
    
    Pre-Emphasis
    114
    
    Configurable Termination Impedance
    115
    
    Txinhibit
    115
    
    Overview
    116
    
    PCI Express Receive Detect Support
    116
    
    Ports and Attributes
    116
    
    Description
    117
    
    Overview
    119
    
    Ports and Attributes
    119
    
    TX Oob/Beacon Signaling
    119
    
    Description
    120
    
    PCI Express Beacon Signaling
    120
    
    SATA OOB Signaling
    120
- Chapter 7 : GTP Receiver (RX)
  
  123
  - Receiver Overview
    123
  - RX Termination and Equalization
    125
    
    Overview
    125
    
    Ports and Attributes
    125
    
    Description
    126
    
    Optional Built-In AC Coupling
    127
    
    Configurable Termination Impedance
    128
    
    Configurable Termination Voltage
    128
    
    Optional Configurable RX Linear Equalization
    129
    
    Overview
    129
    
    RX Oob/Beacon Signaling
    129
    
    Ports and Attributes
    130
    
    Description
    132
    
    Detecting PCI Express Electrical Idle
    132
    
    SATA OOB Detection
    133
    
    Example
    134
    
    Overview
    136
    
    Ports and Attributes
    136
    
    RX Clock Data Recovery (CDR)
    136
    
    Description
    137
    
    CDR Reset
    138
    
    Tuning the CDR
    139
    
    Horizontal Sample Point Shift
    140
    
    Overview
    141
    
    Ports and Attributes
    141
    
    Serial in to Parallel out (SIPO)
    141
    
    Description
    142
    
    Oversampling
    143
    
    Overview
    143
    
    Ports and Attributes
    143
    
    Configuring the 5X Line Rate
    144
    
    Description
    144
    
    Activating and Operating the Oversampling Block
    145
    
    Configuring the PCS Internal Datapath and Clocks
    145
    
    Description
    146
    
    Overview
    146
    
    Ports and Attributes
    146
    
    RX Polarity Control
    146
    
    Overview
    147
    
    Ports and Attributes
    147
    
    PRBS Detection
    147
    
    Configurable Comma Alignment and Detection
    148
    
    Description
    148
    
    Overview
    148
    
    Ports and Attributes
    149
    
    Configuring Comma Patterns
    152
    
    Description
    152
    
    Enabling Comma Alignment
    152
    
    Activating Comma Alignment
    153
    
    Alignment Boundaries
    153
    
    Alignment Status Signals
    153
    
    Manual Alignment
    154
    
    Configurable Loss-Of-Sync State Machine
    155
    
    Overview
    155
    
    Ports and Attributes
    155
    
    Description
    156
    
    Configurable 8B/10B Decoder
    157
    
    Overview
    157
    
    Ports and Attributes
    157
    
    8B/10B Decoder Bit and Byte Order
    158
    
    Description
    158
    
    Enabling the 8B/10B Decoder
    158
    
    Disparity Errors and Not-In-Table Errors
    159
    
    K Characters and 8B/10B Commas
    159
    
    RX Running Disparity
    159
    
    Configurable RX Elastic Buffer and Phase Alignment
    161
    
    Overview
    161
    
    Ports and Attributes
    162
    
    Description
    163
    
    Using the RX Buffer
    163
    
    Using RX Phase Alignment
    164
    
    Bypassing the RX Buffer While Using Built-In Oversampling
    167
    
    Configurable Clock Correction
    168
    
    Overview
    168
    
    Ports and Attributes
    169
    
    Description
    172
    
    Enabling Clock Correction
    172
    
    Setting Clock Correction Sequences
    173
    
    Setting RX Buffer Limits
    173
    
    Clock Correction Options
    174
    
    Monitoring Clock Correction
    174
    
    Configurable Channel Bonding (Lane Deskew)
    175
    
    Overview
    175
    
    Ports and Attributes
    176
    
    Channel Bonding Mode
    178
    
    Connecting Channel Bonding Ports
    178
    
    Description
    178
    
    Enabling Channel Bonding
    178
    
    Setting the Channel Bonding Sequence
    180
    
    Precedence between Channel Bonding and Clock Correction
    181
    
    Setting the Maximum Skew
    181
    
    FPGA RX Interface
    182
    
    Overview
    182
    
    Ports and Attributes
    182
    
    Configuring the Width of the Interface
    183
    
    Description
    183
    
    Connecting RXUSRCLK and RXUSRCLK2
    184
- Chapter 8: Cyclic Redundancy Check (CRC)
  
  187
  - Overview
    187
  - Ports and Attributes
    188
  - Description
    189
    
    Using CRC for Error Checking
    189
    
    The CRC Primitive
    190
    
    Using the CRC Blocks
    191
    
    Integrating the CRC Blocks for RX
    193
    
    Integrating the CRC Blocks for TX
    193
    
    Implementation of the CRC Block
    194
    
    References
    194
- Chapter 9: Loopback
  
  195
  - Overview
    195
  - Ports and Attributes
    196
  - Description
    196
    
    Near-End PCS Loopback
    196
    
    Marginal Conditions and Limitations
    197
    
    Near-End PMA Loopback
    197
    
    Far-End PMA Loopback
    198
    
    Marginal Conditions and Limitations
    198
    
    Far-End PCS Loopback
    199
- Chapter 10 : GTP-To-Board Interface
  
  201
  - Analog Design Guidelines
    201
    
    Overview
    201
    
    Ports and Attributes
    201
    
    Description
    202
    
    Overview
    207
    
    REFCLK Guidelines
    207
    
    Description
    209
    
    GTP Reference Clock Checklist
    209
    
    Oscillator Selection
    209
    
    Sourcing more than One Differential Clock Input Pair from One Oscillator
    209
    
    AC Coupling
    210
    
    Switching between Two Different Reference Clocks
    210
    
    Unused Reference Clock Inputs of GTP_DUAL Tiles for Clock Forwarding
    210
    
    Examples of Vendors and Devices
    211
    
    Overview
    212
    
    Providing Power
    212
    
    Description
    213
    
    Linear Regulator Selection Criteria
    213
    
    Ferrite Selection Guidelines
    214
    
    Regulator Design Guidelines
    214
    
    Capacitor Selection Guidelines
    215
    
    Filter Network Design Guidelines
    215
    
    Special Conditions
    215
    
    Selectio-To-GTP Crosstalk Guidelines
    216
Section 2: Board Level Design

221
- Chapter 11: Design Constraints Overview
  
  223
  - Powering Transceivers
    224
    
    Power Distribution Architecture
    224
    
    Clock Sources
    225
    
    Clock Traces
    225
    
    Filtering
    225
    
    Reference Clock
    225
    
    Regulator Selection
    225
    
    AC Coupling
    226
    
    Coupling
    226
    
    DC Coupling
    226
    
    External Capacitor Value Selection
    226
    
    Selectio to Serial Transceiver Crosstalk Guidelines
    229
- Chapter 12: PCB Materials and Traces
  
  231
  - How Fast Is Fast
    231
  - Dielectric Losses
    231
    
    Relative Permittivity
    231
    
    Choosing the Substrate Material
    232
    
    Loss Tangent
    232
    
    Skin Effect and Resistive Losses
    232
    
    Trace Characteristic Impedance Design
    233
    
    Trace Geometry
    233
    
    Traces
    233
    
    Plane Splits
    235
    
    Return Currents
    235
    
    Trace Routing
    235
    
    Cable
    236
    
    Connectors
    236
    
    Optimal Cable Length
    236
    
    Simulating Lossy Transmission Lines
    236
    
    Skew between Conductors
    236
- Chapter 13: Design of Transitions
  
  237
  - Excess Capacitance and Inductance
    237
  - Time Domain Reflectometry
    237
  - BGA Package
    239
  - SMT Pads
    239
  - Differential Vias
    243
  - P/N Crossover Vias
    245
  - SMA Connectors
    246
  - Backplane Connectors
    246
  - Microstrip/Stripline Bends
    246
- Chapter 14: Guidelines and Examples
  
  251
  - Summary of Guidelines
    251
  - BGA Escape Example
    252
  - HM-Zd Design Example
    252
Section 3: Appendices

255
- Appendix A: MGT to GTP Transceiver Design Migration
  
  257
  - Overview
    257
  - Primary Differences
    257
    
    Mgts Per Device
    257
    
    Clocking
    258
    
    Encoding Support and Clock Multipliers
    259
    
    Serial Rate Support
    259
    
    Board Guidelines
    261
    
    Flexibility
    261
    
    Power Supply Filtering
    261
  - Other Minor Differences
    263
    
    Crc
    263
    
    Loopback
    263
    
    Termination
    263
    
    Defining Clock Correction and Channel Bonding Sequences
    264
    
    RXSTATUS Bus
    264
    
    Serialization
    264
  - Pre-Emphasis, Differential Swing, and Equalization
    264
- Appendix B: Oob/Beacon Signaling
  
  267
  - OOB Signaling in SATA
    267
  - Beacon Signaling in PCI Express
    268
- Appendix C: 8B/10B Valid Characters
  
  270
- Appendix C: 8B/10B Valid Characters
  
  272
- Appendix C: 8B/10B Valid Characters
  
  274
- Appendix C: 8B/10B Valid Characters
  
  276
- Appendix D: DRP Address Map of the GTP_DUAL Tile
  
  280
  - DRP Address by Attribute
    281
  - DRP Address by Bit Location
    296
- Appendix E: Low Latency Design
  
  309
  - GTP Transmitter Latency
    309
  - GTP Receiver Latency
    310
- Appendix F: Advanced Clocking
  
  313
  - Example
    315

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Xilinx Virtex-5 RocketIO GTP Manuals

Xilinx Virtex-5 RocketIO GTP User Manual (316 pages)

Table of Contents

Preface: about this Guide

Section 1: FPGA Level Design

Chapter 1: Introduction to the Rocketio GTP Transceiver

Chapter 2: Rocketio GTP Transceiver Wizard

Chapter 3 : Simulation

Chapter 4: Implementation

Chapter 5: Tile Features

Chapter 6 : GTP Transmitter (TX)

Chapter 7 : GTP Receiver (RX)

Chapter 8: Cyclic Redundancy Check (CRC)

Chapter 9: Loopback

Chapter 10 : GTP-To-Board Interface

Section 2: Board Level Design

Chapter 11: Design Constraints Overview

Chapter 12: PCB Materials and Traces

Chapter 13: Design of Transitions

Chapter 14: Guidelines and Examples

Section 3: Appendices

Appendix A: MGT to GTP Transceiver Design Migration

Appendix B: Oob/Beacon Signaling

Appendix C: 8B/10B Valid Characters

Appendix C: 8B/10B Valid Characters

Appendix C: 8B/10B Valid Characters

Appendix C: 8B/10B Valid Characters

Appendix D: DRP Address Map of the GTP_DUAL Tile

Appendix E: Low Latency Design

Appendix F: Advanced Clocking

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