Xilinx Virtex-6 Manual page 96

Chapter 4: About Design Elements
BUFIO
Primitive: Local Clock Buffer for I/O
Introduction
This design element is a clock buffer. It is simply a clock-in, clock-out buffer. It drives a dedicated clock net
within the I/O column, independent of the global clock resources. Thus, these elements are ideally suited for
source-synchronous data capture (forwarded/receiver clock distribution). They can only be driven by clock
capable I/Os located in the same clock region. They drive the two adjacent I/O clock nets (for a total of up to three
clock regions), as well as the regional clock buffers (BUFR). These elements cannot drive logic resources (CLB,
block RAM, etc.) because the I/O clock network only reaches the I/O column.
Port Descriptions
Port Direction
O Output
I Input
Design Entry Method
Instantiation
Inference
CORE Generator™ and wizards
Macro support
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- BUFIO: I/O Clock Buffer
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
BUFIO_inst : BUFIO
port map (
O => O, -- Buffer output
I => I -- Buffer input
);
-- End of BUFIO_inst instantiation
96
Width Function
1 Clock output
1 Clock input
Recommended
No
No
No
Virtex-6 Libraries Guide for HDL Designs
www.xilinx.com UG623 (v 14.5) March 20, 2013