Xilinx Virtex-6 Manual page 19

Design Entry Method
This unimacro can be instantiated only. It is a parameterizable version of the primitive. Consult the above
Configuration Table in correctly configuring this element to meet your design needs.
Instantiation
Inference
CORE Generator™ and wizards
Macro support
Available Attributes
Attribute Data Type
BRAM_SIZE String
DO_REG Integer
READ_WIDTH, Integer
WRITE_WIDTH
INIT_FILE String
WRITE_MODE String
INIT Hexadecimal
SRVAL Hexadecimal
SIM_MODE String
INIT_00 to Hexadecimal
INIT_FF
INITP_00 to
Hexadecimal
INITP_0F
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Yes
No
No
Recommended
Allowed Values Default
"36Kb", "18Kb" "18Kb"
0, 1 0
1 - 36 1
String NONE
representing file
name and location
"READ_FIRST", "WRITE_FIRST"
"WRITE_FIRST",
"NO_CHANGE"
Any 72-Bit Value All zeros
Any 72-Bit Value All zeroes
"SAFE", "FAST" "SAFE"
Any 256-Bit Value All zeroes
Any 256-Bit Value All zeroes
www.xilinx.com
Chapter 2: About Unimacros
Description
Configures RAM as 36Kb or 18Kb memory.
A value of 1 enables to the output registers
to the RAM enabling quicker clock-to-out
from the RAM at the expense of an added
clock cycle of read latency. A value of 0
allows a read in one clock cycle but will have
slower clock to out timing.
Specifies the size of the DI and DO buses.
The following combinations are allowed:
• READ_WIDTH = WRITE_WIDTH
• If asymmetric, READ_WIDTH and
WRITE_WIDTH must be in the ratio
of 2, or must be values allowed by the
unisim (1, 2, 4, 8, 9, 16, 18, 32, 36, 64, 72)
Name of the file containing initial values.
Specifies write mode to the memory
Specifies the initial value on the output after
configuration.
Specifies the output value of on the DO port
upon the assertion of the synchronous reset
(RST) signal.
This is a simulation only attribute. It
will direct the simulation model to run
in performance-oriented mode when
set to "FAST." Please see the Synthesis
and Simulation Design Guide for more
information.
Allows specification of the initial contents of
the 16Kb or 32Kb data memory array.
Allows specification of the initial contents of
the 2Kb or 4Kb parity data memory array.
19