Xilinx Virtex-6 Manual page 87

VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- BUFGMUX: Global Clock Mux Buffer
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
BUFGMUX_inst : BUFGMUX
port map (
O => O, -- 1-bit output: Clock buffer output
I0 => I0, -- 1-bit input: Clock buffer input (S=0)
I1 => I1, -- 1-bit input: Clock buffer input (S=1)
S => S -- 1-bit input: Clock buffer select
);
-- End of BUFGMUX_inst instantiation
Verilog Instantiation Template
// BUFGMUX: Global Clock Mux Buffer
// Virtex-6
// Xilinx HDL Libraries Guide, version 14.5
BUFGMUX BUFGMUX_inst (
.O(O), // 1-bit output: Clock buffer output
.I0(I0), // 1-bit input: Clock buffer input (S=0)
.I1(I1), // 1-bit input: Clock buffer input (S=1)
.S(S) // 1-bit input: Clock buffer select
);
// End of BUFGMUX_inst instantiation
For More Information
See the Virtex-6 FPGA User Documentation (User Guides and Data
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Sheets).
www.xilinx.com
Chapter 4: About Design Elements
87