Xilinx Virtex-6 Manual page 345

// READ_WIDTH_A/B, WRITE_WIDTH_A/B: Read/write width per port
.READ_WIDTH_A(0),
.READ_WIDTH_B(0),
.WRITE_WIDTH_A(0),
.WRITE_WIDTH_B(0),
// RSTREG_PRIORITY_A, RSTREG_PRIORITY_B: Reset or enable priority ("RSTREG" or "REGCE")
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
// SRVAL_A, SRVAL_B: Set/reset value for output
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
// WriteMode: Value on output upon a write ("WRITE_FIRST", "READ_FIRST", or "NO_CHANGE")
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST")
)
RAMB36E1_inst (
// Cascade Signals: 1-bit (each) output: BRAM cascade ports (to create 64kx1)
.CASCADEOUTA(CASCADEOUTA),
.CASCADEOUTB(CASCADEOUTB),
// ECC Signals: 1-bit (each) output: Error Correction Circuitry ports
.DBITERR(DBITERR),
.ECCPARITY(ECCPARITY),
.RDADDRECC(RDADDRECC),
.SBITERR(SBITERR),
// Port A Data: 32-bit (each) output: Port A data
.DOADO(DOADO),
.DOPADOP(DOPADOP),
// Port B Data: 32-bit (each) output: Port B data
.DOBDO(DOBDO),
.DOPBDOP(DOPBDOP),
// Cascade Signals: 1-bit (each) input: BRAM cascade ports (to create 64kx1)
.CASCADEINA(CASCADEINA),
.CASCADEINB(CASCADEINB),
// ECC Signals: 1-bit (each) input: Error Correction Circuitry ports
.INJECTDBITERR(INJECTDBITERR), // 1-bit input: Inject a double bit error
.INJECTSBITERR(INJECTSBITERR), // 1-bit input: Inject a single bit error
// Port A Address/Control Signals: 16-bit (each) input: Port A address and control signals (read port
// when RAM_MODE="SDP")
.ADDRARDADDR(ADDRARDADDR),
.CLKARDCLK(CLKARDCLK),
.ENARDEN(ENARDEN),
.REGCEAREGCE(REGCEAREGCE),
.RSTRAMARSTRAM(RSTRAMARSTRAM), // 1-bit input: A port set/reset input
.RSTREGARSTREG(RSTREGARSTREG), // 1-bit input: A port register set/reset input
.WEA(WEA),
// Port A Data: 32-bit (each) input: Port A data
.DIADI(DIADI),
.DIPADIP(DIPADIP),
// Port B Address/Control Signals: 16-bit (each) input: Port B address and control signals (write port
// when RAM_MODE="SDP")
.ADDRBWRADDR(ADDRBWRADDR),
.CLKBWRCLK(CLKBWRCLK),
.ENBWREN(ENBWREN),
.REGCEB(REGCEB),
.RSTRAMB(RSTRAMB),
.RSTREGB(RSTREGB),
.WEBWE(WEBWE),
// Port B Data: 32-bit (each) input: Port B data
.DIBDI(DIBDI),
.DIPBDIP(DIPBDIP)
);
// End of RAMB36E1_inst instantiation
For More Information
See the Virtex-6 FPGA User Documentation (User Guides and Data
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
// 1-bit output: A port cascade output
// 1-bit output: B port cascade output
// 1-bit output: double bit error status output
// 8-bit output: generated error correction parity
// 9-bit output: ECC read address
// 1-bit output: Single bit error status output
// 32-bit output: A port data/LSB data output
// 4-bit output: A port parity/LSB parity output
// 32-bit output: B port data/MSB data output
// 4-bit output: B port parity/MSB parity output
// 1-bit input: A port cascade input
// 1-bit input: B port cascade input
// 16-bit input: A port address/Read address input
// 1-bit input: A port clock/Read clock input
// 1-bit input: A port enable/Read enable input
// 1-bit input: A port register enable/Register enable input
// 4-bit input: A port write enable input
// 32-bit input: A port data/LSB data input
// 4-bit input: A port parity/LSB parity input
// 16-bit input: B port address/Write address input
// 1-bit input: B port clock/Write clock input
// 1-bit input: B port enable/Write enable input
// 1-bit input: B port register enable input
// 1-bit input: B port set/reset input
// 1-bit input: B port register set/reset input
// 8-bit input: B port write enable/Write enable input
// 32-bit input: B port data/MSB data input
// 4-bit input: B port parity/MSB parity input
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Chapter 4: About Design Elements
// 0, 1, 2, 4, 9, 18,
// 0, 1, 2, 4, 9, 18,
// 0, 1, 2, 4, 9, 18,
// 0, 1, 2, 4, 9, 18,
Sheets).
// 36, or 72
// or 36
// or 36
// 36, or 72
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