Xilinx Virtex-6 Manual page 308

Chapter 4: About Design Elements
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- RAM32X1S: 32 x 1 posedge write distributed (LUT) RAM
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
RAM32X1S_inst : RAM32X1S
generic map (
INIT => X"00000000")
port map (
O => O, -- RAM output
A0 => A0, -- RAM address[0] input
A1 => A1, -- RAM address[1] input
A2 => A2, -- RAM address[2] input
A3 => A3, -- RAM address[3] input
A4 => A4, -- RAM address[4] input
D => D, -- RAM data input
WCLK => WCLK, -- Write clock input
WE => WE -- Write enable input
);
-- End of RAM32X1S_inst instantiation
Verilog Instantiation Template
// RAM32X1S: 32 x 1 posedge write distributed (LUT) RAM
// Virtex-6
// Xilinx HDL Libraries Guide, version 14.5
RAM32X1S #(
.INIT(32'h00000000)
) RAM32X1S_inst (
.O(O), // RAM output
.A0(A0), // RAM address[0] input
.A1(A1), // RAM address[1] input
.A2(A2), // RAM address[2] input
.A3(A3), // RAM address[3] input
.A4(A4), // RAM address[4] input
.D(D), // RAM data input
.WCLK(WCLK), // Write clock input
.WE(WE) // Write enable input
);
// End of RAM32X1S_inst instantiation
For More Information
See the Virtex-6 FPGA User Documentation (User Guides and Data
308
// Initial contents of RAM
www.xilinx.com
Sheets).
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013