Xilinx Virtex-6 Manual page 372

Chapter 4: About Design Elements
SYSMON
Primitive: System Monitor
Introduction
This design element is built around a 10-bit, 200-kSPS (kilosamples per second) Analog-to-Digital Converter
(ADC). When combined with a number of on-chip sensors, the ADC is used to measure FPGA physical operating
parameters, including on-chip power supply voltages and die temperatures. Access to external voltages is
provided through a dedicated analog-input pair (VP/VN) and 16 user-selectable analog inputs, known as
auxiliary analog inputs (VAUXP[15:0], VAUXN[15:0]). The external analog inputs allow the ADC to monitor
the physical environment of the board or enclosure.
Port Descriptions
Port
ALM[2:0]
BUSY
CHANNEL[4:0]
CONVST
CONVSTCLK
DADDR[6:0]
DCLK
DEN
DI[15:0]
DO[15:0]
DRDY
DWE
EOC
EOS
JTAGBUSY
JTAGLOCKED
JTAGMODIFIED
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Direction Width
Output 3
Output 1
5
Output
Input 1
Input 1
7
Input
Input 1
Input 1
Input 16
Output 16
Output 1
Input 1
Output 1
Output 1
Output 1
Output 1
Output 1
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Function
3-bit output alarm for temp, Vccint and Vccaux
1-bit output ADC busy signal
5-bit output channel selection
1-bit input convert start
1-bit input convert start clock
7-bit input address bus for dynamic reconfig
1-bit input clock for dynamic reconfig
1-bit input enable for dynamic reconfig
16-bit input data bus for dynamic reconfig
16-bit output data bus for dynamic reconfig
1-bit output data ready for dynamic reconfig
1-bit input write enable for dynamic reconfig
1-bit output end of conversion
1-bit output end of sequence
1-bit output JTAG DRP busy
1-bit output DRP port lock
1-bit output JTAG write to DRP
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013