Xilinx Virtex-6 Manual page 173

Available Attributes
Data
Attribute Type
DRIVE Integer
IOSTANDARD String
SLEW String
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- IOBUF: Single-ended Bi-directional Buffer
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
IOBUF_inst : IOBUF
generic map (
DRIVE => 12,
IOSTANDARD => "DEFAULT",
SLEW => "SLOW")
port map (
O => O, -- Buffer output
IO => IO, -- Buffer inout port (connect directly to top-level port)
I => I, -- Buffer input
T => T -- 3-state enable input, high=input, low=output
);
-- End of IOBUF_inst instantiation
Verilog Instantiation Template
// IOBUF: Single-ended Bi-directional Buffer
// All devices
// Xilinx HDL Libraries Guide, version 14.5
IOBUF #(
.DRIVE(12), // Specify the output drive strength
.IOSTANDARD("DEFAULT"), // Specify the I/O standard
.SLEW("SLOW") // Specify the output slew rate
) IOBUF_inst (
.O(O), // Buffer output
.IO(IO), // Buffer inout port (connect directly to top-level port)
.I(I), // Buffer input
.T(T) // 3-state enable input, high=input, low=output
);
// End of IOBUF_inst instantiation
For More Information
See the Virtex-6 FPGA User Documentation (User Guides and Data
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Allowed Values Default
2, 4, 6, 8, 12, 16, 24 12
See Data Sheet "DEFAULT"
"SLOW", "FAST", "SLOW"
"QUIETIO"
www.xilinx.com
Chapter 4: About Design Elements
Description
Selects output drive strength (mA)
for the SelectIO™ buffers that use
the LVTTL, LVCMOS12, LVCMOS15,
LVCMOS18, LVCMOS25, or LVCMOS33
interface I/O standard.
Assigns an I/O standard to the element.
Sets the output rise and fall time. See the
Data Sheet for recommendations of the
best setting for this attribute.
Sheets).
173