I0(I0), // Lut Input; I1(I1), // Lut Input; I2(I2), // Lut Input; I3(I3), // Lut Input - Xilinx Virtex-6 Manual

Design Entry Method
Instantiation
Inference
CORE Generator™ and wizards
Macro support
Available Attributes
Attribute Data Type
INIT
Hexadecimal
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- LUT5_L: 5-input Look-Up Table with local output
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
LUT5_L_inst : LUT5_L
generic map (
INIT => X"00000000") -- Specify LUT Contents
port map (
LO => LO, -- LUT local output
I0 => I0, -- LUT input
I1 => I1, -- LUT input
I2 => I2, -- LUT input
I3 => I3, -- LUT input
I4 => I4 -- LUT input
);
-- End of LUT5_L_inst instantiation
Verilog Instantiation Template
// LUT5_L: 5-input Look-Up Table with local output
// Virtex-6
// Xilinx HDL Libraries Guide, version 14.5
LUT5_L #(
.INIT(32'h0000000) // Specify LUT Contents
) LUT5_L_inst (
.LO(LO), // LUT local output

.I0(I0), // LUT input

.I1(I1), // LUT input

.I2(I2), // LUT input

.I3(I3), // LUT input

.I4(I4) // LUT input
);
// End of LUT5_L_inst instantiation
For More Information
See the Virtex-6 FPGA User Documentation (User Guides and Data
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Yes
Recommended
No
No
Allowed
Values Default
Any 32-Bit Value All zeros
www.xilinx.com
Chapter 4: About Design Elements
Description
Specifies the logic value for the look-up
tables.
Sheets).
231