Xilinx Virtex-6 Manual page 94

Chapter 4: About Design Elements
BUFHCE
Primitive: Clock buffer for a single clocking region with clock enable
Introduction
This element is provided to allow instantiation access to HCLK clock buffer resources. In addition, it allows for
power reduction capabilities through disabling of the clock via clock enable (CE).
Port Descriptions
Port Direction
Input
CE
I Input
O Output
Design Entry Method
Instantiation
Inference
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Macro support
Available Attributes
Attribute Data Type Allowed Values
INIT_OUT DECIMAL
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- BUFHCE: HROW Clock Buffer for a Single Clocking Region with Clock Enable
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
BUFHCE_inst : BUFHCE
generic map (
INIT_OUT => 0 -- Initial output value
)
port map (
O => O, -- 1-bit output: Clock output
CE => CE, -- 1-bit input: Active high enable input
I => I -- 1-bit input: Clock input
94
Width Function
1
Enables propagation of signal from I to O. When low, sets output
to 0.
1 The input to the BUFH
1 The output of the BUFH
Yes
No
No
No
Default
0, 1 0
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Description
Initial output value. Also indicates Stop Low vs Stop
High behavior.
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013