Xilinx Virtex-6 Manual page 60

Chapter 2: About Unimacros
Available Attributes
Attribute Data Type
ALMOST_EMPTY_
Hexadecimal
OFFSET
ALMOST_FULL_ Hexadecimal
OFFSET
DATA_WIDTH Integer
FIFO_SIZE String
FIRST_WORD_ Boolean
FALL_THROUGH
SIM_MODE String
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- FIFO_DUALCLOCK_MACRO: Dual-Clock First-In, First-Out (FIFO) RAM Buffer
--
-- Xilinx HDL Libraries Guide, version 14.5
-- Note - This Unimacro model assumes the port directions to be "downto".
-- Simulation of this model with "to" in the port directions could lead to erroneous results.
-----------------------------------------------------------------
-- DATA_WIDTH | FIFO_SIZE | FIFO Depth | RDCOUNT/WRCOUNT Width --
-- ===========|===========|============|=======================--
-- 37-72 | "36Kb"
-- 19-36 | "36Kb"
-- 19-36 | "18Kb"
-- 10-18 | "36Kb"
-- 10-18 | "18Kb"
-- 5-9 | "36Kb"
-- 5-9 | "18Kb"
-- 1-4 | "36Kb"
-- 1-4 | "18Kb"
-----------------------------------------------------------------
FIFO_DUALCLOCK_MACRO_inst : FIFO_DUALCLOCK_MACRO
generic map (
DEVICE => "VIRTEX6",
ALMOST_FULL_OFFSET => X"0080",
ALMOST_EMPTY_OFFSET => X"0080", -- Sets the almost empty threshold
DATA_WIDTH => 0, -- Valid values are 1-72 (37-72 only valid when FIFO_SIZE="36Kb")
FIFO_SIZE => "18Kb",
FIRST_WORD_FALL_THROUGH => FALSE) -- Sets the FIFO FWFT to TRUE or FALSE
port map (
ALMOSTEMPTY => ALMOSTEMPTY,
ALMOSTFULL => ALMOSTFULL,
DO => DO,
EMPTY => EMPTY,
FULL => FULL,
60
Allowed
Values
13-Bit Value
13-Bit Value
1 - 72
"18Kb", "36Kb"
FALSE, TRUE
"SAFE",
"FAST"
Virtex-6
| 512 |
| 1024 | 10-bit
| 512 |
| 2048 | 11-bit
| 1024 | 10-bit
| 4096 | 12-bit
| 2048 | 11-bit
| 8192 | 13-bit
| 4096 | 12-bit
-- Target Device: "VIRTEX5", "VIRTEX6"
-- Sets almost full threshold
-- Target BRAM, "18Kb" or "36Kb"
-- 1-bit output almost empty
-- 1-bit output almost full
-- Output data, width defined by DATA_WIDTH parameter
-- 1-bit output empty
-- 1-bit output full
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Default Description
All zeros Setting determines the difference between
EMPTY and ALMOSTEMPTY conditions.
Must be set using hexadecimal notation.
All zeros Setting determines the difference between
FULL and ALMOSTFULL conditions. Must
be set using hexadecimal notation.
4 Width of DI/DO bus.
"18Kb" Configures FIFO as 18Kb or 36Kb memory.
FALSE If TRUE, the first word written into the empty
FIFO appears at the FIFO output without
RDEN asserted.
"SAFE" This is a simulation only attribute. It
will direct the simulation model to run in
performance-oriented mode when set to
"FAST". Please see the Synthesis and Simulation
Design Guide for more information.
9-bit --
--
9-bit --
--
--
--
--
--
--
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013