Xilinx Virtex-6 Manual page 285

Port
RST
SHIFTIN1/
SHIFTIN2
SHIFTOUT1/
SHIFTOUT2
TCE
TFB
TQ
T1 - T4
WC
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Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Direction Width Function
Input 1 The reset input causes the outputs of all data flip-flops in the
CLK and CLKDIV domains to be driven Low asynchronously.
OSERDES circuits running in the CLK domain where timing
is critical use an internal, dedicated circuit to retime the RST
input to produce a reset signal synchronous to the CLK domain.
Similarly, there is a dedicated circuit to retime the RST input
to produce a reset signal synchronous to the CLKDIV domain.
Because there are OSERDES circuits that retime the RST input,
the user is only required to provide a reset pulse to the RST
input that meets timing on the CLKDIV frequency domain
(synchronous to CLKDIV). Therefore, RST should be driven High
for a minimum of one CLKDIV cycle. When building an interface
consisting of multiple OSERDES ports, all OSERDES ports must be
synchronized. The internal retiming of the RST input is designed
so that all OSERDES blocks that receive the same reset pulse come
out of reset synchronized with one another.
Input 1 Cascade Input for data input expansion. Connect to SHIFTOUT1/2
of slave.
Output 1 Cascade out for data input expansion. Connect to SHIFTIN1/2
of master.
Input 1
TCE is an active High clock enable for the 3-state control path.
1
Output This port is the 3-state control output of the OSERDES module
sent to the IODELAY. When used, this port connects the output of
the 3-state parallel-to-serial converter to the control/3-state input
of the IODELAY.
Output 1
This port is the 3-state control output of the OSERDES module.
When used, this port connects the output of the 3-state
parallel-to-serial converter to the control/3-state input of the IOB.
Input 1 Parallel 3-State Inputs - All parallel 3-state signals enter the
OSERDES module through ports T1 to T4. The ports are connected
to the FPGA fabric, and can be configured as one, two, or four bits.
Input 1 The WC port is a part of the dedicated logic for the
MEMORY_DDR3 mode. The write command is issued when
switching from writing to reading data. WC is only available in
MEMORY_DDR3 mode for DDR3 applications. When not using
MEMORY_DDR3 mode, connect this port to GND.
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