Xilinx Virtex-6 Manual page 338

Chapter 4: About Design Elements
Attribute
RAM_EXTENSION_A
RAM_EXTENSION_B
RAM_MODE
READ_WIDTH_A
READ_WIDTH_B
RSTREG_PRIORITY_A
RSTREG_PRIORITY_B
SRVAL_A
SRVAL_B
WRITEMODE
338
Data Type Allowed Values
String "NONE",
"LOWER",
"UPPER"
String "NONE",
"LOWER",
"UPPER"
String "TDP", "SDP"
Integer 0, 1, 2, 4, 9, 18, 36, 72
Integer 0, 1, 2, 4, 9, 18, 36, 72
String "RSTREG",
"REGCE"
String "RSTREG",
"REGCE"
Hexa-
Any 36 bit Value
decimal
Hexa- Any 36 bit Value
decimal
String "WRITE_FIRST",
"READ_FIRST",
"NO_CHANGE",
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Default Description
"NONE" Selects port A cascade mode. If not
cascading two block RAMs to form
a 72K x 1 RAM, set to "NONE". If
cascading RAMs, set to either "UPPER"
or "LOWER" to indicate relative RAM
location for proper configuration of the
RAM. Not used if RAM_MODE=SDP.
"NONE" Selects port B cascade mode. If not
cascading two block RAMs to form
a 72K x 1 RAM, set to "NONE". If
cascading RAMs, set to either "UPPER"
or "LOWER" to indicate relative RAM
location for proper configuration of the
RAM. Not used if RAM_MODE=SDP.
"TDP" Selects simple dual port (SDP) or true
dual port (TDP) mode.
0 Specifies the desired data width for a
read on port A, including parity bits.
This value must be 0 if the port is not
used. Otherwise, it should be set to the
desired port width.
0
Specifies the desired data width for a
read on port B, including parity bits.
This value must be 0 if the port is not
used. Otherwise, it should be set to the
desired port width.
"RSTREG" Selects register priority for RSTREG
or REGCE. Applies to port A in TDP
mode and up to 36 lower bits (including
parity bits) in SDP mode.
"RSTREG" Selects register priority for RSTREG or
REGCE. Applies to port B in TDP mode
and upper bits (including parity bits)
in SDP mode.
All zeros Specifies the output value of the RAM
upon assertion of the synchronous
reset (RSTREG) signal.
All zeros Specifies the output value of the RAM
upon assertion of the synchronous
reset (RSTREG) signal.
"WRITE_ Specifies output behavior of the port
FIRST" being written to:
• "WRITE_FIRST" - written value
appears on output port of the RAM
• "READ_FIRST" - previous RAM
contents for that memory location
appear on the output port
• "NO_CHANGE" - previous value
on the output port remains the
same.
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013