Xilinx Virtex-6 Manual page 305

Available Attributes
Attribute Data Type
INIT
Hexadecimal
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- RAM32X1D: 32 x 1 positive edge write, asynchronous read
-- dual-port distributed RAM
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
RAM32X1D_inst : RAM32X1D
generic map (
INIT => X"00000000") -- Initial contents of RAM
port map (
DPO => DPO, -- Read-only 1-bit data output
SPO => SPO, -- R/W 1-bit data output
A0 => A0, -- R/W address[0] input bit
A1 => A1, -- R/W address[1] input bit
A2 => A2, -- R/W address[2] input bit
A3 => A3, -- R/W address[3] input bit
A4 => A4, -- R/W address[4] input bit
D => D, -- Write 1-bit data input
DPRA0 => DPRA0, -- Read-only address[0] input bit
DPRA1 => DPRA1, -- Read-only address[1] input bit
DPRA2 => DPRA2, -- Read-only address[2] input bit
DPRA3 => DPRA3, -- Read-only address[3] input bit
DPRA4 => DPRA4, -- Read-only address[4] input bit
WCLK => WCLK, -- Write clock input
WE => WE -- Write enable input
);
-- End of RAM32X1D_inst instantiation
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Allowed
Values Default
Any 32-Bit All Zeros
Value
www.xilinx.com
Chapter 4: About Design Elements
Descriptions
Initializes ROMs, RAMs, registers, and look-up
tables.
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