Xilinx Virtex-6 Manual page 100

Chapter 4: About Design Elements
Available Attributes
Data
Attribute Type
BUFR_DIVIDE
String
SIM_DEVICE String
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- BUFR: Regional Clock Buffer for I/O and Logic Resources within a Clock Region
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
BUFR_inst : BUFR
generic map (
BUFR_DIVIDE => "BYPASS",
SIM_DEVICE => "VIRTEX6")
port map (
O => O, -- 1-bit output: Clock output port
CE => CE, -- 1-bit input: Active high, clock enable (Divided modes only)
CLR => CLR, -- 1-bit input: Active high, asynchronous clear (Divided mode only)
I => I -- 1-bit input: Clock buffer input driven by an IBUFG, MMCM or local interconnect
);
-- End of BUFR_inst instantiation
Verilog Instantiation Template
// BUFR: Regional Clock Buffer for I/O and Logic Resources within a Clock Region
// Virtex-6
// Xilinx HDL Libraries Guide, version 14.5
BUFR #(
.BUFR_DIVIDE("BYPASS"), // Values: "BYPASS, 1, 2, 3, 4, 5, 6, 7, 8"
.SIM_DEVICE("VIRTEX6")
)
BUFR_inst (
.O(O), // 1-bit output: Clock output port
.CE(CE), // 1-bit input: Active high, clock enable (Divided modes only)
.CLR(CLR), // 1-bit input: Active high, asynchronous clear (Divided modes only)
.I(I) // 1-bit input: Clock buffer input driven by an IBUFG, MMCM or local interconnect
);
// End of BUFR_inst instantiation
For More Information
See the Virtex-6 FPGA User Documentation (User Guides and Data
100
Allowed_Values
"BYPASS", "1", "2", "3",
"4", "5", "6", "7", "8"
"VIRTEX4", VIRTEX5",
"VIRTEX6"
-- "BYPASS", "1", "2", "3", "4", "5", "6", "7", "8"
-- Must be set to "VIRTEX6"
// Must be set to "VIRTEX6"
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Default Description
"BYPASS" Defines whether the output clock is a
divided version of input clock.
"VIRTEX4" Determine the CE latency for BUFR.
Sheets).
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013