Xilinx Virtex-6 Manual page 132

Chapter 4: About Design Elements
Port
DOP[3:0]
EMPTY
FULL
RDEN
REGCE
RST
RSTREG
WRCLK,
RDCLK
WRCOUNT,
RDCOUNT
WREN
WRERR,
RDERR
Design Entry Method
Instantiation
Inference
CORE Generator™ and wizards
Macro support
Available Attributes
Attribute
ALMOST_EMPTY_
OFFSET
ALMOST_FULL_
OFFSET
DATA_WIDTH
DO_REG
EN_SYN
FIFO_MODE
132
Direction Width
Output 4
Output 1
Output 1
Input 1
Input 1
Input 1
Input 1
Input 1
Output 12
Input 1
Output 1
Data Type Allowed Values Default
Hexa- 13'h0000 to
decimal
13'h8191
Hexa- 13'h0000 to
decimal
13'h8191
Integer 4, 9, 18, 36
Integer 1, 0
Boolean FALSE, TRUE
String "FIFO18",
"FIFO18_36"
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Function
FIFO parity data output bus.
Active High logic to indicate that the FIFO is currently
empty.
Active High logic indicates that the FIFO is full.
Active High FIFO read enable.
Output register clock enable for pipelined synchronous
FIFO.
Active High (FIFO logic) asynchronous reset (for
dual-clock FIFO), synchronous reset (synchronous
FIFO) for 3 CLK cycles.
Output register synchronous set/reset.
FIFO read and write clocks (positive edge triggered).
FIFO write/read pointer.
Active High FIFO write enable.
• WRERR indicates that a write occurred while the
FIFO was full.
• RDERR indicates that a read occurred while the
FIFO was empty.
Yes
No
No
Recommended
Description
13'h0080 Specifies the amount of data
contents in the RAM to trigger the
ALMOST_EMPTY flag.
13'h0080 Specifies the amount of data
contents in the RAM to trigger the
ALMOST_FULL flag.
4
Specifies the desired data width for
the FIFO.
1 Data pipeline register for EN_SYN.
FALSE Specifies whether the FIFO is operating
in either dual-clock (two independent
clocks) or synchronous (single
clock) mode. Dual-clock must use
DO_REG=1.
"FIFO18" Selects FIFO18 or FIFO18_36 mode.
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013