Xilinx Virtex-6 Manual page 148

Chapter 4: About Design Elements
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- IBUF: Single-ended Input Buffer
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
IBUF_inst : IBUF
generic map (
IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT")
port map (
O => O, -- Buffer output
I => I -- Buffer input (connect directly to top-level port)
);
-- End of IBUF_inst instantiation
Verilog Instantiation Template
// IBUF: Single-ended Input Buffer
// Virtex-6
// Xilinx HDL Libraries Guide, version 14.5
IBUF #(
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT")
)IBUF_inst (
.O(O), // Buffer output
.I(I) // Buffer input (connect directly to top-level port)
);
// End of IBUF_inst instantiation
For More Information
See the Virtex-6 FPGA User Documentation (User Guides and Data
148
// Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
// Specify the input I/O standard
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Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013