Xilinx Virtex-6 Manual page 324

Chapter 4: About Design Elements
RAMB18E1
Primitive: 18K-bit Configurable Synchronous Block RAM
Introduction
Virtex®-6 devices contain several block RAM memories that can be configured as FIFOs, automatic error
correction RAM, or general-purpose 36 kb or 18 kb RAM/ROM memories. These block RAM memories offer fast
and flexible storage of large amounts of on-chip data. This element allows access to the block RAM in the 18 kb
configuration. This element can be configured and used as a 1-bit wide by 16K deep to an 18-bit wide by 1029-bit
deep true dual port RAM. This element can also be configured as a 36-bit wide by 512 deep simple dual port
RAM. Both read and write operations are fully synchronous to the supplied clock(s) in the component. However,
the READ and WRITE ports can operate fully independently and asynchronously to each other, accessing the
same memory array. When configured in the wider data width modes, byte-enable write operations are possible,
and an optional output register can be used to reduce the clock-to-out times of the RAM.
Port Descriptions
Port
ADDRARDADDR[13:0]
ADDRBWRADDR[13:0]
CLKARDCLK
324
Direction Width Function
Input 14
Port A address input bus/Read address input bus.
Input 14
Port B address input bus/Write address input bus.
Input 1 Port A clock input/Read clock input.
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UG623 (v 14.5) March 20, 2013