Verilog Instantiation Template - Xilinx Virtex-6 Manual

VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- LUT6_2: 6-input 2 output Look-Up Table
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
LUT6_2_inst : LUT6_2
generic map (
INIT => X"0000000000000000") -- Specify LUT Contents
port map (
O6 => O6, -- 6/5-LUT output (1-bit)
O5 => O5, -- 5-LUT output (1-bit)
I0 => I0, -- LUT input (1-bit)
I1 => I1, -- LUT input (1-bit)
I2 => I2, -- LUT input (1-bit)
I3 => I3, -- LUT input (1-bit)
I4 => I4, -- LUT input (1-bit)
I5 => I5 -- LUT input (1-bit)
);
-- End of LUT6_2_inst instantiation

Verilog Instantiation Template

// LUT6_2: 6-input, 2 output Look-Up Table
// Virtex-6
// Xilinx HDL Libraries Guide, version 14.5
LUT6_2 #(
.INIT(64'h0000000000000000) // Specify LUT Contents
) LUT6_2_inst (
.O6(O6), // 1-bit LUT6 output
.O5(O5), // 1-bit lower LUT5 output
.I0(I0), // 1-bit LUT input
.I1(I1), // 1-bit LUT input
.I2(I2), // 1-bit LUT input
.I3(I3), // 1-bit LUT input
.I4(I4), // 1-bit LUT input
.I5(I5) // 1-bit LUT input (fast MUX select only available to O6 output)
);
// End of LUT6_2_inst instantiation
For More Information
See the Virtex-6 FPGA User Documentation (User Guides and Data
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Sheets).
www.xilinx.com
Chapter 4: About Design Elements
239