Xilinx Virtex-6 Manual page 18

Chapter 2: About Unimacros
WRITE_WIDTH READ_WIDTH
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9 - 5
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18-10 18-10
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BRAM_SIZE ADDR
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15
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18Kb 10
11
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18Kb 11
11
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14
18Kb 12
12
12
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18Kb
13
13
13
14
14
18Kb
14
14
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Virtex-6 Libraries Guide for HDL Designs
www.xilinx.com
WE
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UG623 (v 14.5) March 20, 2013