Xilinx Virtex-6 Manual page 17

Configuration Table
WRITE_WIDTH READ_WIDTH
37 - 72 37 - 72
36 - 19
18 - 10
9 - 5
4 - 3
2
1
36 - 19 36 - 19
18-10
9 - 5
4 - 3
2
1
18 - 10 36 - 19
18-10
9 - 5
4 - 3
2
1
9 - 5 36-19
18-10
9 - 5
4 - 3
2
1
4 - 3 36-19
18-10
9 - 5
4 - 3
2
1
2 36-19
18-10
9 - 5
4 - 3
2
1
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
BRAM_SIZE ADDR
36Kb 9
10
11
12
13
14
15
36Kb 10
11
12
13
14
15
11
36Kb
11
12
13
14
15
36Kb 12
12
12
13
14
15
36Kb 13
13
13
13
14
15
36Kb 14
14
14
14
14
15
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Chapter 2: About Unimacros
WE
8
4
2
1
1
1
17