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Chapter 2:
Configuration Interfaces
3.
4.
5.
6.
7.
8.
There are a number of important considerations for ganged serial configuration:
Startup Sequencing (GTS)
GTS should be released before DONE or during the same cycle as DONE to ensure all
devices are operational when all DONE pins have been released.
Disable the Active DONE Driver On for All Devices
For ganged serial configuration, the active DONE driver must be disabled for all devices if
the DONE pins are tied together, because there can be variations in the startup sequencing
of each device. A pull-up resistor is therefore required on the common DONE signal.
-g DriveDone:no (BitGen option, all devices)
Connect All DONE Pins if Using a Master Device
It is important to connect the DONE pins for all devices in ganged serial configuration if
one FPGA is used as the Master device. Failing to connect the DONE pins can cause
configuration to fail for individual devices in this case. If all devices are set for Slave serial
mode, the DONE pins can be disconnected (if the external CCLK source continues toggling
until all DONE pins go High).
For debugging purposes, it is often helpful to have a way of disconnecting individual
DONE pins from the common DONE signal.
DONE Pin Rise Time
After all DONE pins are released, the DONE pin should rise from logic 0 to logic 1 in one
CCLK cycle. If additional time is required for the DONE signal to rise, the BitGen
donepipe option can be set for all devices in the serial daisy chain.
Configuration Clock (CCLK) as Clock Signal for Board Layout
The CCLK signal is an LVCMOS fast 12 mA driver (LVCMOS_P12.) Signal integrity issues
on the CCLK signal can cause configuration to fail. (Typical failure mode: DONE Low,
INIT_B High.) Therefore, careful attention to signal integrity, including signal integrity
simulation with IBIS, is recommended.
Signal Fanout
Special care must be taken in assuring good signal integrity when using ganged serial
configuration. Signal integrity simulation is recommended.
38
The BitGen startup clock setting must be set for CCLK for serial configuration.
The PROM in this diagram represents one or more Xilinx serial PROMs. Multiple serial
PROMs can be cascaded to increase the overall configuration storage capacity.
The .bit file must be reformatted into a PROM file before it can be stored on the serial
PROM. Refer to the
"Generating PROM Files"
On XC17V00 devices, the reset polarity is programmable. RESET should be set for
active Low when using an XC17V00 device in this setup.
For ganged serial configuration, all devices must be identical (same IDCODE) and
must be configured with the same bitstream.
The CCLK net requires Thevenin parallel termination. See
Configuration Clock (CCLK)," page
www.xilinx.com
section.
"Board Layout for
34.
Virtex-4 FPGA Configuration User Guide
UG071 (v1.12) June 2, 2017
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