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PSTCLK
DSCLK
DSI
BDM State
Machine
DSO
DSCLK and DSI are synchronized inputs. DSCLK acts as a pseudo clock enable and is sampled, along
with DSI, on the rising edge of PSTCLK. DSO is delayed from the DSCLK-enabled PSTCLK rising edge
(registered after a BDM state machine state change). All events in the debug module's serial state machine
are based on the PSTCLK rising edge. DSCLK must also be sampled low (on a positive edge of PSTCLK)
between each bit exchange. The msb is sent first. Because DSO changes state based on an internally
recognized rising edge of DSCLK, DSO cannot be used to indicate the start of a serial transfer. The
development system must count clock cycles in a given transfer. C0–C4 are described as:
•
C0: Set the state of the DSI bit
•
C1: First synchronization cycle for DSI (DSCLK is high)
•
C2: Second synchronization cycle for DSI (DSCLK is high)
•
C3: BDM state machine changes state depending upon DSI and whether the entire input data
transfer has been transmitted
•
C4: DSO changes to next value
A not-ready response can be ignored except during a memory-referencing
cycle. Otherwise, the debug module can accept a new serial transfer after 32
processor clock periods.
32.5.2.1
Receive Packet Format
The basic receive packet consists of 16 data bits and 1 status bit
.
16
15
14
S
Freescale Semiconductor
C0
C1
Current
Current State
Past
Figure 32-13. Maximum BDM Serial Interface Timing
13
12
11
10
Figure 32-14. Receive BDM Packet
MCF52277 Reference Manual, Rev. 1
C2
C3
C4
NOTE
9
8
7
6
Data
Next
Next State
Current
5
4
3
2
Debug Module
1
0
32-21
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