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Figure 30-3
shows an example of a QSPI clocking and data transfer.
QSPI_CLK
QSPI_DOUT
15
msb
QSPI_DIN
15
QSPI_CS
QMR[CPOL] = 0
QMR[CPHA] = 1
QCR[CONT] = 0
30.3.2
QSPI Delay Register (QDLYR)
The QDLYR is used to initiate master mode transfers and to set various delay parameters.
Address: 0xFC05_C004 (QDLYR)
15
14
13
R
SPE
W
Reset
0
0
Field
15
QSPI enable. When set, the QSPI initiates transfers in master mode by executing commands in the command RAM.
SPE
The QSPI clears this bit automatically when a transfer completes. The user can also clear this bit to abort transfer
unless QIR[ABRTL] is set. The recommended method for aborting transfers is to set QWR[HALT].
14–8
QSPI_CLK delay. When the DSCK bit in the command RAM is set this field determines the length of the delay from
QCD
assertion of the chip selects to valid QSPI_CLK transition. See
setting this bit field.
7–0
Delay after transfer. When the DT bit in the command RAM is set this field determines the length of delay after the
DTL
serial transfer.
Freescale Semiconductor
14
13
12
11
10
14
13
12
11
10
A
Figure 30-3. QSPI Clocking and Data Transfer Example
12
11
10
QCD
0
0
0
1
Figure 30-4. QSPI Delay Register (QDLYR)
Table 30-4. QDLYR Field Descriptions
MCF5329 Reference Manual, Rev 3
Queued Serial Peripheral Interface (QSPI)
9
8
7
6
5
4
9
8
7
6
5
4
Chip selects are active low
A = QDLYR[QCD]
B = QDLYR[DTL]
9
8
7
6
5
0
0
0
0
0
Description
Section 30.4.3, "Transfer Delays"
3
2
1
0
3
2
1
0
B
Access: User read/write
4
3
2
1
DTL
0
0
1
0
for information on
0
0
30-5
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